0001 # SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/serial/qcom,msm-uartdm.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm MSM Serial UARTDM
0008
0009 maintainers:
0010 - Andy Gross <agross@kernel.org>
0011 - Bjorn Andersson <bjorn.andersson@linaro.org>
0012 - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
0013
0014 description: |
0015 The MSM serial UARTDM hardware is designed for high-speed use cases where the
0016 transmit and/or receive channels can be offloaded to a dma-engine. From a
0017 software perspective it's mostly compatible with the MSM serial UART except
0018 that it supports reading and writing multiple characters at a time.
0019
0020 Note:: Aliases may be defined to ensure the correct ordering of the UARTs.
0021 The alias serialN will result in the UART being assigned port N. If any
0022 serialN alias exists, then an alias must exist for each enabled UART. The
0023 serialN aliases should be in a .dts file instead of in a .dtsi file.
0024
0025 properties:
0026 compatible:
0027 items:
0028 - enum:
0029 - qcom,msm-uartdm-v1.1
0030 - qcom,msm-uartdm-v1.2
0031 - qcom,msm-uartdm-v1.3
0032 - qcom,msm-uartdm-v1.4
0033 - const: qcom,msm-uartdm
0034
0035 clocks:
0036 maxItems: 2
0037
0038 clock-names:
0039 items:
0040 - const: core
0041 - const: iface
0042
0043 dmas:
0044 maxItems: 2
0045
0046 dma-names:
0047 items:
0048 - const: tx
0049 - const: rx
0050
0051 interrupts:
0052 maxItems: 1
0053
0054 qcom,rx-crci:
0055 $ref: /schemas/types.yaml#/definitions/uint32
0056 description:
0057 Identificator for Client Rate Control Interface to be used with RX DMA
0058 channel. Required when using DMA for reception with UARTDM v1.3 and
0059 below.
0060
0061 qcom,tx-crci:
0062 $ref: /schemas/types.yaml#/definitions/uint32
0063 description:
0064 Identificator for Client Rate Control Interface to be used with TX DMA
0065 channel. Required when using DMA for transmission with UARTDM v1.3 and
0066 below.
0067
0068 reg:
0069 minItems: 1
0070 items:
0071 - description: Main control registers
0072 - description: An optional second register location shall specify the GSBI control region.
0073
0074 required:
0075 - compatible
0076 - clock-names
0077 - clocks
0078 - interrupts
0079 - reg
0080
0081 unevaluatedProperties: false
0082
0083 allOf:
0084 - $ref: /schemas/serial/serial.yaml#
0085
0086 - if:
0087 properties:
0088 compatible:
0089 contains:
0090 const: qcom,msm-uartdm-v1.3
0091 then:
0092 properties:
0093 reg:
0094 minItems: 2
0095 else:
0096 properties:
0097 reg:
0098 maxItems: 1
0099
0100 examples:
0101 - |
0102 #include <dt-bindings/interrupt-controller/arm-gic.h>
0103
0104 serial@f991e000 {
0105 compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm";
0106 reg = <0xf991e000 0x1000>;
0107 interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
0108 clocks = <&blsp1_uart2_apps_cxc>, <&blsp1_ahb_cxc>;
0109 clock-names = "core", "iface";
0110 dmas = <&dma0 0>, <&dma0 1>;
0111 dma-names = "tx", "rx";
0112 };
