0001 Device tree bindings for Marvell PXA SSP ports
0002
0003 Required properties:
0004
0005 - compatible: Must be one of
0006 mrvl,pxa25x-ssp
0007 mvrl,pxa25x-nssp
0008 mrvl,pxa27x-ssp
0009 mrvl,pxa3xx-ssp
0010 mvrl,pxa168-ssp
0011 mrvl,pxa910-ssp
0012 mrvl,ce4100-ssp
0013
0014 - reg: The memory base
0015 - dmas: Two dma phandles, one for rx, one for tx
0016 - dma-names: Must be "rx", "tx"
0017
0018
0019 Example for PXA3xx:
0020
0021 ssp0: ssp@41000000 {
0022 compatible = "mrvl,pxa3xx-ssp";
0023 reg = <0x41000000 0x40>;
0024 ssp-id = <1>;
0025 interrupts = <24>;
0026 clock-names = "pxa27x-ssp.0";
0027 dmas = <&dma 13
0028 &dma 14>;
0029 dma-names = "rx", "tx";
0030 };
0031
0032 ssp1: ssp@41700000 {
0033 compatible = "mrvl,pxa3xx-ssp";
0034 reg = <0x41700000 0x40>;
0035 ssp-id = <2>;
0036 interrupts = <16>;
0037 clock-names = "pxa27x-ssp.1";
0038 dmas = <&dma 15
0039 &dma 16>;
0040 dma-names = "rx", "tx";
0041 };
0042
0043 ssp2: ssp@41900000 {
0044 compatibl3 = "mrvl,pxa3xx-ssp";
0045 reg = <0x41900000 0x40>;
0046 ssp-id = <3>;
0047 interrupts = <0>;
0048 clock-names = "pxa27x-ssp.2";
0049 dmas = <&dma 66
0050 &dma 67>;
0051 dma-names = "rx", "tx";
0052 };
0053
0054 ssp3: ssp@41a00000 {
0055 compatible = "mrvl,pxa3xx-ssp";
0056 reg = <0x41a00000 0x40>;
0057 ssp-id = <4>;
0058 interrupts = <13>;
0059 clock-names = "pxa27x-ssp.3";
0060 dmas = <&dma 2
0061 &dma 3>;
0062 dma-names = "rx", "tx";
0063 };
0064
