0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/serial/cdns,uart.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Cadence UART Controller Device Tree Bindings
0008
0009 maintainers:
0010 - Michal Simek <michal.simek@xilinx.com>
0011
0012 allOf:
0013 - $ref: /schemas/serial.yaml#
0014
0015 properties:
0016 compatible:
0017 oneOf:
0018 - description: UART controller for Zynq-7xxx SoC
0019 items:
0020 - const: xlnx,xuartps
0021 - const: cdns,uart-r1p8
0022 - description: UART controller for Zynq Ultrascale+ MPSoC
0023 items:
0024 - const: xlnx,zynqmp-uart
0025 - const: cdns,uart-r1p12
0026
0027 reg:
0028 maxItems: 1
0029
0030 interrupts:
0031 maxItems: 1
0032
0033 clocks:
0034 maxItems: 2
0035
0036 clock-names:
0037 items:
0038 - const: uart_clk
0039 - const: pclk
0040
0041 cts-override:
0042 description: |
0043 Override the CTS modem status signal. This signal will
0044 always be reported as active instead of being obtained
0045 from the modem status register. Define this if your serial
0046 port does not use this pin.
0047 type: boolean
0048
0049 required:
0050 - compatible
0051 - reg
0052 - interrupts
0053 - clocks
0054 - clock-names
0055
0056 unevaluatedProperties: false
0057
0058 examples:
0059 - |
0060 uart0: serial@e0000000 {
0061 compatible = "xlnx,xuartps", "cdns,uart-r1p8";
0062 clocks = <&clkc 23>, <&clkc 40>;
0063 clock-names = "uart_clk", "pclk";
0064 reg = <0xE0000000 0x1000>;
0065 interrupts = <0 27 4>;
0066 };
