0001 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/serial/8250.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
0008
0009 maintainers:
0010 - devicetree@vger.kernel.org
0011
0012 allOf:
0013 - $ref: serial.yaml#
0014 - if:
0015 anyOf:
0016 - required:
0017 - aspeed,lpc-io-reg
0018 - required:
0019 - aspeed,lpc-interrupts
0020 - required:
0021 - aspeed,sirq-polarity-sense
0022 then:
0023 properties:
0024 compatible:
0025 const: aspeed,ast2500-vuart
0026 - if:
0027 properties:
0028 compatible:
0029 const: mrvl,mmp-uart
0030 then:
0031 properties:
0032 reg-shift:
0033 const: 2
0034 required:
0035 - reg-shift
0036 - if:
0037 not:
0038 properties:
0039 compatible:
0040 items:
0041 - enum:
0042 - ns8250
0043 - ns16450
0044 - ns16550
0045 - ns16550a
0046 then:
0047 anyOf:
0048 - required: [ clock-frequency ]
0049 - required: [ clocks ]
0050
0051 properties:
0052 compatible:
0053 oneOf:
0054 - const: ns8250
0055 - const: ns16450
0056 - const: ns16550
0057 - const: ns16550a
0058 - const: ns16850
0059 - const: aspeed,ast2400-vuart
0060 - const: aspeed,ast2500-vuart
0061 - const: intel,xscale-uart
0062 - const: mrvl,pxa-uart
0063 - const: nuvoton,wpcm450-uart
0064 - const: nuvoton,npcm750-uart
0065 - const: nuvoton,npcm845-uart
0066 - const: nvidia,tegra20-uart
0067 - const: nxp,lpc3220-uart
0068 - items:
0069 - enum:
0070 - exar,xr16l2552
0071 - exar,xr16l2551
0072 - exar,xr16l2550
0073 - const: ns8250
0074 - items:
0075 - enum:
0076 - altr,16550-FIFO32
0077 - altr,16550-FIFO64
0078 - altr,16550-FIFO128
0079 - fsl,16550-FIFO64
0080 - fsl,ns16550
0081 - andestech,uart16550
0082 - nxp,lpc1850-uart
0083 - opencores,uart16550-rtlsvn105
0084 - ti,da830-uart
0085 - const: ns16550a
0086 - items:
0087 - enum:
0088 - ns16750
0089 - cavium,octeon-3860-uart
0090 - xlnx,xps-uart16550-2.00.b
0091 - ralink,rt2880-uart
0092 - enum:
0093 - ns16550 # Deprecated, unless the FIFO really is broken
0094 - ns16550a
0095 - items:
0096 - enum:
0097 - ralink,mt7620a-uart
0098 - ralink,rt3052-uart
0099 - ralink,rt3883-uart
0100 - const: ralink,rt2880-uart
0101 - enum:
0102 - ns16550 # Deprecated, unless the FIFO really is broken
0103 - ns16550a
0104 - items:
0105 - enum:
0106 - mediatek,mt7622-btif
0107 - mediatek,mt7623-btif
0108 - const: mediatek,mtk-btif
0109 - items:
0110 - const: mrvl,mmp-uart
0111 - const: intel,xscale-uart
0112 - items:
0113 - enum:
0114 - nvidia,tegra30-uart
0115 - nvidia,tegra114-uart
0116 - nvidia,tegra124-uart
0117 - nvidia,tegra210-uart
0118 - nvidia,tegra186-uart
0119 - nvidia,tegra194-uart
0120 - nvidia,tegra234-uart
0121 - const: nvidia,tegra20-uart
0122
0123 reg:
0124 maxItems: 1
0125
0126 interrupts:
0127 maxItems: 1
0128
0129 clock-frequency: true
0130
0131 clocks:
0132 maxItems: 1
0133
0134 resets:
0135 maxItems: 1
0136
0137 current-speed:
0138 $ref: /schemas/types.yaml#/definitions/uint32
0139 description: The current active speed of the UART.
0140
0141 reg-offset:
0142 $ref: /schemas/types.yaml#/definitions/uint32
0143 description: |
0144 Offset to apply to the mapbase from the start of the registers.
0145
0146 reg-shift:
0147 description: Quantity to shift the register offsets by.
0148
0149 reg-io-width:
0150 description: |
0151 The size (in bytes) of the IO accesses that should be performed on the
0152 device. There are some systems that require 32-bit accesses to the
0153 UART (e.g. TI davinci).
0154
0155 used-by-rtas:
0156 type: boolean
0157 description: |
0158 Set to indicate that the port is in use by the OpenFirmware RTAS and
0159 should not be registered.
0160
0161 no-loopback-test:
0162 type: boolean
0163 description: |
0164 Set to indicate that the port does not implement loopback test mode.
0165
0166 fifo-size:
0167 $ref: /schemas/types.yaml#/definitions/uint32
0168 description: The fifo size of the UART.
0169
0170 auto-flow-control:
0171 type: boolean
0172 description: |
0173 One way to enable automatic flow control support. The driver is
0174 allowed to detect support for the capability even without this
0175 property.
0176
0177 tx-threshold:
0178 description: |
0179 Specify the TX FIFO low water indication for parts with programmable
0180 TX FIFO thresholds.
0181
0182 overrun-throttle-ms:
0183 description: |
0184 How long to pause uart rx when input overrun is encountered.
0185
0186 rts-gpios: true
0187 cts-gpios: true
0188 dtr-gpios: true
0189 dsr-gpios: true
0190 rng-gpios: true
0191 dcd-gpios: true
0192
0193 aspeed,sirq-polarity-sense:
0194 $ref: /schemas/types.yaml#/definitions/phandle-array
0195 description: |
0196 Phandle to aspeed,ast2500-scu compatible syscon alongside register
0197 offset and bit number to identify how the SIRQ polarity should be
0198 configured. One possible data source is the LPC/eSPI mode bit. Only
0199 applicable to aspeed,ast2500-vuart.
0200 deprecated: true
0201
0202 aspeed,lpc-io-reg:
0203 $ref: '/schemas/types.yaml#/definitions/uint32'
0204 description: |
0205 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
0206
0207 aspeed,lpc-interrupts:
0208 $ref: "/schemas/types.yaml#/definitions/uint32-array"
0209 minItems: 2
0210 maxItems: 2
0211 description: |
0212 A 2-cell property describing the VUART SIRQ number and SIRQ
0213 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
0214 applicable to aspeed,ast2500-vuart.
0215
0216 required:
0217 - reg
0218 - interrupts
0219
0220 unevaluatedProperties: false
0221
0222 examples:
0223 - |
0224 serial@80230000 {
0225 compatible = "ns8250";
0226 reg = <0x80230000 0x100>;
0227 interrupts = <10>;
0228 reg-shift = <2>;
0229 clock-frequency = <48000000>;
0230 };
0231 - |
0232 #include <dt-bindings/gpio/gpio.h>
0233 serial@49042000 {
0234 compatible = "andestech,uart16550", "ns16550a";
0235 reg = <0x49042000 0x400>;
0236 interrupts = <80>;
0237 clock-frequency = <48000000>;
0238 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
0239 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
0240 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
0241 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
0242 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
0243 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
0244 };
0245 - |
0246 #include <dt-bindings/clock/aspeed-clock.h>
0247 #include <dt-bindings/interrupt-controller/irq.h>
0248 serial@1e787000 {
0249 compatible = "aspeed,ast2500-vuart";
0250 reg = <0x1e787000 0x40>;
0251 reg-shift = <2>;
0252 interrupts = <8>;
0253 clocks = <&syscon ASPEED_CLK_APB>;
0254 no-loopback-test;
0255 aspeed,lpc-io-reg = <0x3f8>;
0256 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
0257 };
0258
0259 ...
