0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2022 Microchip Technology, Inc. and its subsidiaries
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/rtc/atmel,at91sam9260-rtt.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Atmel AT91 RTT Device Tree Bindings
0009
0010 allOf:
0011 - $ref: "rtc.yaml#"
0012
0013 maintainers:
0014 - Alexandre Belloni <alexandre.belloni@bootlin.com>
0015
0016 properties:
0017 compatible:
0018 oneOf:
0019 - items:
0020 - const: atmel,at91sam9260-rtt
0021 - items:
0022 - const: microchip,sam9x60-rtt
0023 - const: atmel,at91sam9260-rtt
0024 - items:
0025 - const: microchip,sama7g5-rtt
0026 - const: microchip,sam9x60-rtt
0027 - const: atmel,at91sam9260-rtt
0028
0029 reg:
0030 maxItems: 1
0031
0032 interrupts:
0033 maxItems: 1
0034
0035 clocks:
0036 maxItems: 1
0037
0038 atmel,rtt-rtc-time-reg:
0039 $ref: /schemas/types.yaml#/definitions/phandle-array
0040 items:
0041 - items:
0042 - description: Phandle to the GPBR node.
0043 - description: Offset within the GPBR block.
0044 description:
0045 Should encode the GPBR register used to store the time base when the
0046 RTT is used as an RTC. The first cell should point to the GPBR node
0047 and the second one encodes the offset within the GPBR block (or in
0048 other words, the GPBR register used to store the time base).
0049
0050 required:
0051 - compatible
0052 - reg
0053 - interrupts
0054 - clocks
0055 - atmel,rtt-rtc-time-reg
0056
0057 unevaluatedProperties: false
0058
0059 examples:
0060 - |
0061 #include <dt-bindings/interrupt-controller/irq.h>
0062
0063 rtc@fffffd20 {
0064 compatible = "atmel,at91sam9260-rtt";
0065 reg = <0xfffffd20 0x10>;
0066 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
0067 clocks = <&clk32k>;
0068 atmel,rtt-rtc-time-reg = <&gpbr 0x0>;
0069 };
