0001 TI Davinci DSP devices
0002 =======================
0003
0004 Binding status: Unstable - Subject to changes for DT representation of clocks
0005 and resets
0006
0007 The TI Davinci family of SoCs usually contains a TI DSP Core sub-system that
0008 is used to offload some of the processor-intensive tasks or algorithms, for
0009 achieving various system level goals.
0010
0011 The processor cores in the sub-system usually contain additional sub-modules
0012 like L1 and/or L2 caches/SRAMs, an Interrupt Controller, an external memory
0013 controller, a dedicated local power/sleep controller etc. The DSP processor
0014 core used in Davinci SoCs is usually a C674x DSP CPU.
0015
0016 DSP Device Node:
0017 ================
0018 Each DSP Core sub-system is represented as a single DT node.
0019
0020 Required properties:
0021 --------------------
0022 The following are the mandatory properties:
0023
0024 - compatible: Should be one of the following,
0025 "ti,da850-dsp" for DSPs on OMAP-L138 SoCs
0026
0027 - reg: Should contain an entry for each value in 'reg-names'.
0028 Each entry should have the memory region's start address
0029 and the size of the region, the representation matching
0030 the parent node's '#address-cells' and '#size-cells' values.
0031
0032 - reg-names: Should contain strings with the following names, each
0033 representing a specific internal memory region or a
0034 specific register space,
0035 "l2sram", "l1pram", "l1dram", "host1cfg", "chipsig_base"
0036
0037 - interrupts: Should contain the interrupt number used to receive the
0038 interrupts from the DSP. The value should follow the
0039 interrupt-specifier format as dictated by the
0040 'interrupt-parent' node.
0041
0042 - memory-region: phandle to the reserved memory node to be associated
0043 with the remoteproc device. The reserved memory node
0044 can be a CMA memory node, and should be defined as
0045 per the bindings in
0046 Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt
0047
0048
0049 Example:
0050 --------
0051
0052 /* DSP Reserved Memory node */
0053 reserved-memory {
0054 #address-cells = <1>;
0055 #size-cells = <1>;
0056 ranges;
0057
0058 dsp_memory_region: dsp-memory@c3000000 {
0059 compatible = "shared-dma-pool";
0060 reg = <0xc3000000 0x1000000>;
0061 reusable;
0062 };
0063 };
0064
0065 /* DSP node */
0066 {
0067 dsp: dsp@11800000 {
0068 compatible = "ti,da850-dsp";
0069 reg = <0x11800000 0x40000>,
0070 <0x11e00000 0x8000>,
0071 <0x11f00000 0x8000>,
0072 <0x01c14044 0x4>,
0073 <0x01c14174 0x8>;
0074 reg-names = "l2sram", "l1pram", "l1dram", "host1cfg",
0075 "chipsig";
0076 interrupt-parent = <&intc>;
0077 interrupts = <28>;
0078 memory-region = <&dsp_memory_region>;
0079 };
0080 };
