bindings/remoteproc/qcom%2Csdm845-adsp-pil.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/remoteproc/qcom,sdm845-adsp-pil.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm SDM845 ADSP Peripheral Image Loader
0008
0009 maintainers:
0010   - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description:
0013   This document defines the binding for a component that loads and boots firmware
0014   on the Qualcomm Technology Inc. ADSP.
0015
0016 properties:
0017   compatible:
0018     enum:
0019       - qcom,sdm845-adsp-pil
0020
0021   reg:
0022     maxItems: 1
0023     description:
0024       The base address and size of the qdsp6ss register
0025
0026   interrupts:
0027     items:
0028       - description: Watchdog interrupt
0029       - description: Fatal interrupt
0030       - description: Ready interrupt
0031       - description: Handover interrupt
0032       - description: Stop acknowledge interrupt
0033
0034   interrupt-names:
0035     items:
0036       - const: wdog
0037       - const: fatal
0038       - const: ready
0039       - const: handover
0040       - const: stop-ack
0041
0042   clocks:
0043     items:
0044       - description: XO clock
0045       - description: SWAY clock
0046       - description: LPASS AHBS AON clock
0047       - description: LPASS AHBM AON clock
0048       - description: QDSP XO clock
0049       - description: Q6SP6SS SLEEP clock
0050       - description: Q6SP6SS CORE clock
0051
0052   clock-names:
0053     items:
0054       - const: xo
0055       - const: sway_cbcr
0056       - const: lpass_ahbs_aon_cbcr
0057       - const: lpass_ahbm_aon_cbcr
0058       - const: qdsp6ss_xo
0059       - const: qdsp6ss_sleep
0060       - const: qdsp6ss_core
0061
0062   power-domains:
0063     items:
0064       - description: CX power domain
0065
0066   resets:
0067     items:
0068       - description: PDC AUDIO SYNC RESET
0069       - description: CC LPASS restart
0070
0071   reset-names:
0072     items:
0073       - const: pdc_sync
0074       - const: cc_lpass
0075
0076   memory-region:
0077     maxItems: 1
0078     description: Reference to the reserved-memory for the Hexagon core
0079
0080   qcom,halt-regs:
0081     $ref: /schemas/types.yaml#/definitions/phandle-array
0082     description:
0083       Phandle reference to a syscon representing TCSR followed by the
0084       three offsets within syscon for q6, modem and nc halt registers.
0085
0086   qcom,smem-states:
0087     $ref: /schemas/types.yaml#/definitions/phandle-array
0088     description: States used by the AP to signal the Hexagon core
0089     items:
0090       - description: Stop the modem
0091
0092   qcom,smem-state-names:
0093     description: The names of the state bits used for SMP2P output
0094     items:
0095       - const: stop
0096
0097 required:
0098   - compatible
0099   - reg
0100   - interrupts
0101   - interrupt-names
0102   - clocks
0103   - clock-names
0104   - power-domains
0105   - resets
0106   - reset-names
0107   - qcom,halt-regs
0108   - memory-region
0109   - qcom,smem-states
0110   - qcom,smem-state-names
0111
0112 additionalProperties: false
0113
0114 examples:
0115   - |
0116     #include <dt-bindings/interrupt-controller/arm-gic.h>
0117     #include <dt-bindings/clock/qcom,rpmh.h>
0118     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0119     #include <dt-bindings/clock/qcom,lpass-sdm845.h>
0120     #include <dt-bindings/power/qcom-rpmpd.h>
0121     #include <dt-bindings/reset/qcom,sdm845-pdc.h>
0122     #include <dt-bindings/reset/qcom,sdm845-aoss.h>
0123     remoteproc@17300000 {
0124         compatible = "qcom,sdm845-adsp-pil";
0125         reg = <0x17300000 0x40c>;
0126
0127         interrupts-extended = <&intc GIC_SPI 162 IRQ_TYPE_EDGE_RISING>,
0128                 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0129                 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0130                 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0131                 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
0132         interrupt-names = "wdog", "fatal", "ready",
0133                 "handover", "stop-ack";
0134
0135         clocks = <&rpmhcc RPMH_CXO_CLK>,
0136                  <&gcc GCC_LPASS_SWAY_CLK>,
0137                  <&lpasscc LPASS_Q6SS_AHBS_AON_CLK>,
0138                  <&lpasscc LPASS_Q6SS_AHBM_AON_CLK>,
0139                  <&lpasscc LPASS_QDSP6SS_XO_CLK>,
0140                  <&lpasscc LPASS_QDSP6SS_SLEEP_CLK>,
0141                  <&lpasscc LPASS_QDSP6SS_CORE_CLK>;
0142         clock-names = "xo", "sway_cbcr",
0143                 "lpass_ahbs_aon_cbcr",
0144                 "lpass_ahbm_aon_cbcr", "qdsp6ss_xo",
0145                 "qdsp6ss_sleep", "qdsp6ss_core";
0146
0147         power-domains = <&rpmhpd SDM845_CX>;
0148
0149         resets = <&pdc_reset PDC_AUDIO_SYNC_RESET>,
0150                  <&aoss_reset AOSS_CC_LPASS_RESTART>;
0151         reset-names = "pdc_sync", "cc_lpass";
0152
0153         qcom,halt-regs = <&tcsr_mutex_regs 0x22000>;
0154
0155         memory-region = <&pil_adsp_mem>;
0156
0157         qcom,smem-states = <&adsp_smp2p_out 0>;
0158         qcom,smem-state-names = "stop";
0159     };