0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/remoteproc/qcom,sc7280-wpss-pil.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm SC7280 WPSS Peripheral Image Loader
0008
0009 maintainers:
0010 - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description:
0013 This document defines the binding for a component that loads and boots firmware
0014 on the Qualcomm Technology Inc. WPSS.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - qcom,sc7280-wpss-pil
0020
0021 reg:
0022 maxItems: 1
0023 description:
0024 The base address and size of the qdsp6ss register
0025
0026 interrupts:
0027 items:
0028 - description: Watchdog interrupt
0029 - description: Fatal interrupt
0030 - description: Ready interrupt
0031 - description: Handover interrupt
0032 - description: Stop acknowledge interrupt
0033 - description: Shutdown acknowledge interrupt
0034
0035 interrupt-names:
0036 items:
0037 - const: wdog
0038 - const: fatal
0039 - const: ready
0040 - const: handover
0041 - const: stop-ack
0042 - const: shutdown-ack
0043
0044 clocks:
0045 items:
0046 - description: GCC WPSS AHB BDG Master clock
0047 - description: GCC WPSS AHB clock
0048 - description: GCC WPSS RSCP clock
0049 - description: XO clock
0050
0051 clock-names:
0052 items:
0053 - const: ahb_bdg
0054 - const: ahb
0055 - const: rscp
0056 - const: xo
0057
0058 power-domains:
0059 items:
0060 - description: CX power domain
0061 - description: MX power domain
0062
0063 power-domain-names:
0064 items:
0065 - const: cx
0066 - const: mx
0067
0068 resets:
0069 items:
0070 - description: AOSS restart
0071 - description: PDC SYNC
0072
0073 reset-names:
0074 items:
0075 - const: restart
0076 - const: pdc_sync
0077
0078 memory-region:
0079 maxItems: 1
0080 description: Reference to the reserved-memory for the Hexagon core
0081
0082 firmware-name:
0083 $ref: /schemas/types.yaml#/definitions/string
0084 description:
0085 The name of the firmware which should be loaded for this remote
0086 processor.
0087
0088 qcom,halt-regs:
0089 $ref: /schemas/types.yaml#/definitions/phandle-array
0090 description:
0091 Phandle reference to a syscon representing TCSR followed by the
0092 three offsets within syscon for q6, modem and nc halt registers.
0093
0094 qcom,qmp:
0095 $ref: /schemas/types.yaml#/definitions/phandle
0096 description: Reference to the AOSS side-channel message RAM.
0097
0098 qcom,smem-states:
0099 $ref: /schemas/types.yaml#/definitions/phandle-array
0100 description: States used by the AP to signal the Hexagon core
0101 items:
0102 - description: Stop the modem
0103
0104 qcom,smem-state-names:
0105 description: The names of the state bits used for SMP2P output
0106 const: stop
0107
0108 glink-edge:
0109 $ref: qcom,glink-edge.yaml#
0110 description:
0111 Qualcomm G-Link subnode which represents communication edge, channels
0112 and devices related to the ADSP.
0113
0114 properties:
0115 interrupts:
0116 items:
0117 - description: IRQ from WPSS to GLINK
0118
0119 mboxes:
0120 items:
0121 - description: Mailbox for communication between APPS and WPSS
0122
0123 label:
0124 items:
0125 - const: wpss
0126
0127 apr: false
0128 fastrpc: false
0129
0130 required:
0131 - compatible
0132 - reg
0133 - interrupts
0134 - interrupt-names
0135 - clocks
0136 - clock-names
0137 - power-domains
0138 - power-domain-names
0139 - resets
0140 - reset-names
0141 - qcom,halt-regs
0142 - memory-region
0143 - qcom,qmp
0144 - qcom,smem-states
0145 - qcom,smem-state-names
0146 - glink-edge
0147
0148 additionalProperties: false
0149
0150 examples:
0151 - |
0152 #include <dt-bindings/interrupt-controller/arm-gic.h>
0153 #include <dt-bindings/clock/qcom,gcc-sc7280.h>
0154 #include <dt-bindings/clock/qcom,rpmh.h>
0155 #include <dt-bindings/power/qcom-rpmpd.h>
0156 #include <dt-bindings/reset/qcom,sdm845-aoss.h>
0157 #include <dt-bindings/reset/qcom,sdm845-pdc.h>
0158 #include <dt-bindings/mailbox/qcom-ipcc.h>
0159 remoteproc@8a00000 {
0160 compatible = "qcom,sc7280-wpss-pil";
0161 reg = <0x08a00000 0x10000>;
0162
0163 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>,
0164 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0165 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0166 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0167 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
0168 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
0169 interrupt-names = "wdog", "fatal", "ready", "handover",
0170 "stop-ack", "shutdown-ack";
0171
0172 clocks = <&gcc GCC_WPSS_AHB_BDG_MST_CLK>,
0173 <&gcc GCC_WPSS_AHB_CLK>,
0174 <&gcc GCC_WPSS_RSCP_CLK>,
0175 <&rpmhcc RPMH_CXO_CLK>;
0176 clock-names = "ahb_bdg", "ahb",
0177 "rscp", "xo";
0178
0179 power-domains = <&rpmhpd SC7280_CX>,
0180 <&rpmhpd SC7280_MX>;
0181 power-domain-names = "cx", "mx";
0182
0183 memory-region = <&wpss_mem>;
0184
0185 qcom,qmp = <&aoss_qmp>;
0186
0187 qcom,smem-states = <&wpss_smp2p_out 0>;
0188 qcom,smem-state-names = "stop";
0189
0190 resets = <&aoss_reset AOSS_CC_WCSS_RESTART>,
0191 <&pdc_reset PDC_WPSS_SYNC_RESET>;
0192 reset-names = "restart", "pdc_sync";
0193
0194 qcom,halt-regs = <&tcsr_mutex 0x37000>;
0195
0196 glink-edge {
0197 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS
0198 IPCC_MPROC_SIGNAL_GLINK_QMP
0199 IRQ_TYPE_EDGE_RISING>;
0200 mboxes = <&ipcc IPCC_CLIENT_WPSS
0201 IPCC_MPROC_SIGNAL_GLINK_QMP>;
0202
0203 label = "wpss";
0204 qcom,remote-pid = <13>;
0205 };
0206 };
