bindings/remoteproc/qcom%2Cqcs404-cdsp-pil.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/remoteproc/qcom,qcs404-cdsp-pil.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Qualcomm QCS404 CDSP Peripheral Image Loader
0008
0009 maintainers:
0010   - Bjorn Andersson <bjorn.andersson@linaro.org>
0011
0012 description:
0013   This document defines the binding for a component that loads and boots firmware
0014   on the Qualcomm Technology Inc. CDSP (Compute DSP).
0015
0016 properties:
0017   compatible:
0018     enum:
0019       - qcom,qcs404-cdsp-pil
0020
0021   reg:
0022     maxItems: 1
0023     description:
0024       The base address and size of the qdsp6ss register
0025
0026   interrupts:
0027     items:
0028       - description: Watchdog interrupt
0029       - description: Fatal interrupt
0030       - description: Ready interrupt
0031       - description: Handover interrupt
0032       - description: Stop acknowledge interrupt
0033
0034   interrupt-names:
0035     items:
0036       - const: wdog
0037       - const: fatal
0038       - const: ready
0039       - const: handover
0040       - const: stop-ack
0041
0042   clocks:
0043     items:
0044       - description: XO clock
0045       - description: SWAY clock
0046       - description: TBU clock
0047       - description: BIMC clock
0048       - description: AHB AON clock
0049       - description: Q6SS SLAVE clock
0050       - description: Q6SS MASTER clock
0051       - description: Q6 AXIM clock
0052
0053   clock-names:
0054     items:
0055       - const: xo
0056       - const: sway
0057       - const: tbu
0058       - const: bimc
0059       - const: ahb_aon
0060       - const: q6ss_slave
0061       - const: q6ss_master
0062       - const: q6_axim
0063
0064   power-domains:
0065     items:
0066       - description: CX power domain
0067
0068   resets:
0069     items:
0070       - description: AOSS restart
0071
0072   reset-names:
0073     items:
0074       - const: restart
0075
0076   memory-region:
0077     maxItems: 1
0078     description: Reference to the reserved-memory for the Hexagon core
0079
0080   qcom,halt-regs:
0081     $ref: /schemas/types.yaml#/definitions/phandle-array
0082     description:
0083       Phandle reference to a syscon representing TCSR followed by the
0084       three offsets within syscon for q6, modem and nc halt registers.
0085
0086   qcom,smem-states:
0087     $ref: /schemas/types.yaml#/definitions/phandle-array
0088     description: States used by the AP to signal the Hexagon core
0089     items:
0090       - description: Stop the modem
0091
0092   qcom,smem-state-names:
0093     description: The names of the state bits used for SMP2P output
0094     items:
0095       - const: stop
0096
0097 required:
0098   - compatible
0099   - reg
0100   - interrupts
0101   - interrupt-names
0102   - clocks
0103   - clock-names
0104   - power-domains
0105   - resets
0106   - reset-names
0107   - qcom,halt-regs
0108   - memory-region
0109   - qcom,smem-states
0110   - qcom,smem-state-names
0111
0112 additionalProperties: false
0113
0114 examples:
0115   - |
0116     #include <dt-bindings/interrupt-controller/arm-gic.h>
0117     #include <dt-bindings/clock/qcom,gcc-qcs404.h>
0118     #include <dt-bindings/power/qcom-rpmpd.h>
0119     #include <dt-bindings/clock/qcom,turingcc-qcs404.h>
0120     remoteproc@b00000 {
0121         compatible = "qcom,qcs404-cdsp-pil";
0122         reg = <0x00b00000 0x4040>;
0123
0124         interrupts-extended = <&intc GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
0125                               <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
0126                               <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
0127                               <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
0128                               <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
0129         interrupt-names = "wdog", "fatal", "ready",
0130                           "handover", "stop-ack";
0131
0132         clocks = <&xo_board>,
0133                  <&gcc GCC_CDSP_CFG_AHB_CLK>,
0134                  <&gcc GCC_CDSP_TBU_CLK>,
0135                  <&gcc GCC_BIMC_CDSP_CLK>,
0136                  <&turingcc TURING_WRAPPER_AON_CLK>,
0137                  <&turingcc TURING_Q6SS_AHBS_AON_CLK>,
0138                  <&turingcc TURING_Q6SS_AHBM_AON_CLK>,
0139                  <&turingcc TURING_Q6SS_Q6_AXIM_CLK>;
0140         clock-names = "xo",
0141                       "sway",
0142                       "tbu",
0143                       "bimc",
0144                       "ahb_aon",
0145                       "q6ss_slave",
0146                       "q6ss_master",
0147                       "q6_axim";
0148
0149         power-domains = <&rpmhpd SDM845_CX>;
0150
0151         resets = <&gcc GCC_CDSP_RESTART>;
0152         reset-names = "restart";
0153
0154         qcom,halt-regs = <&tcsr 0x19004>;
0155
0156         memory-region = <&cdsp_fw_mem>;
0157
0158         qcom,smem-states = <&cdsp_smp2p_out 0>;
0159         qcom,smem-state-names = "stop";
0160     };