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0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/remoteproc/ingenic,vpu.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006 
0007 title: Ingenic Video Processing Unit bindings
0008 
0009 description:
0010   Inside the Video Processing Unit (VPU) of the recent JZ47xx SoCs from
0011   Ingenic is a second Xburst MIPS CPU very similar to the main core.
0012   This document describes the devicetree bindings for this auxiliary
0013   processor.
0014 
0015 maintainers:
0016   - Paul Cercueil <paul@crapouillou.net>
0017 
0018 properties:
0019   compatible:
0020     const: ingenic,jz4770-vpu-rproc
0021 
0022   reg:
0023     items:
0024       - description: aux registers
0025       - description: tcsm0 registers
0026       - description: tcsm1 registers
0027       - description: sram registers
0028 
0029   reg-names:
0030     items:
0031       - const: aux
0032       - const: tcsm0
0033       - const: tcsm1
0034       - const: sram
0035 
0036   clocks:
0037     items:
0038       - description: aux clock
0039       - description: vpu clock
0040 
0041   clock-names:
0042     items:
0043       - const: aux
0044       - const: vpu
0045 
0046   interrupts:
0047     maxItems: 1
0048 
0049 required:
0050   - compatible
0051   - reg
0052   - reg-names
0053   - clocks
0054   - clock-names
0055   - interrupts
0056 
0057 additionalProperties: false
0058 
0059 examples:
0060   - |
0061     #include <dt-bindings/clock/ingenic,jz4770-cgu.h>
0062 
0063     vpu: video-decoder@132a0000 {
0064       compatible = "ingenic,jz4770-vpu-rproc";
0065 
0066       reg = <0x132a0000 0x20>, /* AUX */
0067             <0x132b0000 0x4000>, /* TCSM0 */
0068             <0x132c0000 0xc000>, /* TCSM1 */
0069             <0x132f0000 0x7000>; /* SRAM */
0070       reg-names = "aux", "tcsm0", "tcsm1", "sram";
0071 
0072       clocks = <&cgu JZ4770_CLK_AUX>, <&cgu JZ4770_CLK_VPU>;
0073       clock-names = "aux", "vpu";
0074 
0075       interrupt-parent = <&cpuintc>;
0076       interrupts = <3>;
0077     };