0001 Spreadtrum PWM controller
0002
0003 Spreadtrum SoCs PWM controller provides 4 PWM channels.
0004
0005 Required properties:
0006 - compatible : Should be "sprd,ums512-pwm".
0007 - reg: Physical base address and length of the controller's registers.
0008 - clocks: The phandle and specifier referencing the controller's clocks.
0009 - clock-names: Should contain following entries:
0010 "pwmn": used to derive the functional clock for PWM channel n (n range: 0 ~ 3).
0011 "enablen": for PWM channel n enable clock (n range: 0 ~ 3).
0012 - #pwm-cells: Should be 2. See pwm.yaml in this directory for a description of
0013 the cells format.
0014
0015 Optional properties:
0016 - assigned-clocks: Reference to the PWM clock entries.
0017 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
0018
0019 Example:
0020 pwms: pwm@32260000 {
0021 compatible = "sprd,ums512-pwm";
0022 reg = <0 0x32260000 0 0x10000>;
0023 clock-names = "pwm0", "enable0",
0024 "pwm1", "enable1",
0025 "pwm2", "enable2",
0026 "pwm3", "enable3";
0027 clocks = <&aon_clk CLK_PWM0>, <&aonapb_gate CLK_PWM0_EB>,
0028 <&aon_clk CLK_PWM1>, <&aonapb_gate CLK_PWM1_EB>,
0029 <&aon_clk CLK_PWM2>, <&aonapb_gate CLK_PWM2_EB>,
0030 <&aon_clk CLK_PWM3>, <&aonapb_gate CLK_PWM3_EB>;
0031 assigned-clocks = <&aon_clk CLK_PWM0>,
0032 <&aon_clk CLK_PWM1>,
0033 <&aon_clk CLK_PWM2>,
0034 <&aon_clk CLK_PWM3>;
0035 assigned-clock-parents = <&ext_26m>,
0036 <&ext_26m>,
0037 <&ext_26m>,
0038 <&ext_26m>;
0039 #pwm-cells = <2>;
0040 };
