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OSCL-LXR

 
 

    


0001 MediaTek PWM controller
0002 
0003 Required properties:
0004  - compatible: should be "mediatek,<name>-pwm":
0005    - "mediatek,mt2712-pwm": found on mt2712 SoC.
0006    - "mediatek,mt6795-pwm": found on mt6795 SoC.
0007    - "mediatek,mt7622-pwm": found on mt7622 SoC.
0008    - "mediatek,mt7623-pwm": found on mt7623 SoC.
0009    - "mediatek,mt7628-pwm": found on mt7628 SoC.
0010    - "mediatek,mt7629-pwm": found on mt7629 SoC.
0011    - "mediatek,mt8183-pwm": found on mt8183 SoC.
0012    - "mediatek,mt8195-pwm", "mediatek,mt8183-pwm": found on mt8195 SoC.
0013    - "mediatek,mt8365-pwm": found on mt8365 SoC.
0014    - "mediatek,mt8516-pwm": found on mt8516 SoC.
0015  - reg: physical base address and length of the controller's registers.
0016  - #pwm-cells: must be 2. See pwm.yaml in this directory for a description of
0017    the cell format.
0018  - clocks: phandle and clock specifier of the PWM reference clock.
0019  - clock-names: must contain the following, except for MT7628 which
0020                 has no clocks
0021    - "top": the top clock generator
0022    - "main": clock used by the PWM core
0023    - "pwm1-3": the three per PWM clocks for mt8365
0024    - "pwm1-8": the eight per PWM clocks for mt2712
0025    - "pwm1-6": the six per PWM clocks for mt7622
0026    - "pwm1-5": the five per PWM clocks for mt7623
0027    - "pwm1"  : the PWM1 clock for mt7629
0028  - pinctrl-names: Must contain a "default" entry.
0029  - pinctrl-0: One property must exist for each entry in pinctrl-names.
0030    See pinctrl/pinctrl-bindings.txt for details of the property values.
0031 
0032 Optional properties:
0033 - assigned-clocks: Reference to the PWM clock entries.
0034 - assigned-clock-parents: The phandle of the parent clock of PWM clock.
0035 
0036 Example:
0037         pwm0: pwm@11006000 {
0038                 compatible = "mediatek,mt7623-pwm";
0039                 reg = <0 0x11006000 0 0x1000>;
0040                 #pwm-cells = <2>;
0041                 clocks = <&topckgen CLK_TOP_PWM_SEL>,
0042                          <&pericfg CLK_PERI_PWM>,
0043                          <&pericfg CLK_PERI_PWM1>,
0044                          <&pericfg CLK_PERI_PWM2>,
0045                          <&pericfg CLK_PERI_PWM3>,
0046                          <&pericfg CLK_PERI_PWM4>,
0047                          <&pericfg CLK_PERI_PWM5>;
0048                 clock-names = "top", "main", "pwm1", "pwm2",
0049                               "pwm3", "pwm4", "pwm5";
0050                 pinctrl-names = "default";
0051                 pinctrl-0 = <&pwm0_pins>;
0052         };