0001 Tegra SoC PWFM controller
0002
0003 Required properties:
0004 - compatible: Must be:
0005 - "nvidia,tegra20-pwm": for Tegra20
0006 - "nvidia,tegra30-pwm", "nvidia,tegra20-pwm": for Tegra30
0007 - "nvidia,tegra114-pwm", "nvidia,tegra20-pwm": for Tegra114
0008 - "nvidia,tegra124-pwm", "nvidia,tegra20-pwm": for Tegra124
0009 - "nvidia,tegra132-pwm", "nvidia,tegra20-pwm": for Tegra132
0010 - "nvidia,tegra210-pwm", "nvidia,tegra20-pwm": for Tegra210
0011 - "nvidia,tegra186-pwm": for Tegra186
0012 - "nvidia,tegra194-pwm": for Tegra194
0013 - reg: physical base address and length of the controller's registers
0014 - #pwm-cells: should be 2. See pwm.yaml in this directory for a description of
0015 the cells format.
0016 - clocks: Must contain one entry, for the module clock.
0017 See ../clocks/clock-bindings.txt for details.
0018 - resets: Must contain an entry for each entry in reset-names.
0019 See ../reset/reset.txt for details.
0020 - reset-names: Must include the following entries:
0021 - pwm
0022
0023 Optional properties:
0024 ============================
0025 In some of the interface like PWM based regulator device, it is required
0026 to configure the pins differently in different states, especially in suspend
0027 state of the system. The configuration of pin is provided via the pinctrl
0028 DT node as detailed in the pinctrl DT binding document
0029 Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
0030
0031 The PWM node will have following optional properties.
0032 pinctrl-names: Pin state names. Must be "default" and "sleep".
0033 pinctrl-0: phandle for the default/active state of pin configurations.
0034 pinctrl-1: phandle for the sleep state of pin configurations.
0035
0036 Example:
0037
0038 pwm: pwm@7000a000 {
0039 compatible = "nvidia,tegra20-pwm";
0040 reg = <0x7000a000 0x100>;
0041 #pwm-cells = <2>;
0042 clocks = <&tegra_car 17>;
0043 resets = <&tegra_car 17>;
0044 reset-names = "pwm";
0045 };
0046
0047
0048 Example with the pin configuration for suspend and resume:
0049 =========================================================
0050 Suppose pin PE7 (On Tegra210) interfaced with the regulator device and
0051 it requires PWM output to be tristated when system enters suspend.
0052 Following will be DT binding to achieve this:
0053
0054 #include <dt-bindings/pinctrl/pinctrl-tegra.h>
0055
0056 pinmux@700008d4 {
0057 pwm_active_state: pwm_active_state {
0058 pe7 {
0059 nvidia,pins = "pe7";
0060 nvidia,tristate = <TEGRA_PIN_DISABLE>;
0061 };
0062 };
0063
0064 pwm_sleep_state: pwm_sleep_state {
0065 pe7 {
0066 nvidia,pins = "pe7";
0067 nvidia,tristate = <TEGRA_PIN_ENABLE>;
0068 };
0069 };
0070 };
0071
0072 pwm@7000a000 {
0073 /* Mandatory PWM properties */
0074 pinctrl-names = "default", "sleep";
0075 pinctrl-0 = <&pwm_active_state>;
0076 pinctrl-1 = <&pwm_sleep_state>;
0077 };
