0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: http://devicetree.org/schemas/pwm/microchip,corepwm.yaml#
0006 $schema: http://devicetree.org/meta-schemas/core.yaml#
0007
0008 title: Microchip IP corePWM controller bindings
0009
0010 maintainers:
0011 - Conor Dooley <conor.dooley@microchip.com>
0012
0013 description: |
0014 corePWM is an 16 channel pulse width modulator FPGA IP
0015
0016 https://www.microsemi.com/existing-parts/parts/152118
0017
0018 allOf:
0019 - $ref: pwm.yaml#
0020
0021 properties:
0022 compatible:
0023 items:
0024 - const: microchip,corepwm-rtl-v4
0025
0026 reg:
0027 maxItems: 1
0028
0029 clocks:
0030 maxItems: 1
0031
0032 "#pwm-cells":
0033 const: 2
0034
0035 microchip,sync-update-mask:
0036 description: |
0037 Depending on how the IP is instantiated, there are two modes of operation.
0038 In synchronous mode, all channels are updated at the beginning of the PWM period,
0039 and in asynchronous mode updates happen as the control registers are written.
0040 A 16 bit wide "SHADOW_REG_EN" parameter of the IP core controls whether synchronous
0041 mode is possible for each channel, and is set by the bitstream programmed to the
0042 FPGA. If the IP core is instantiated with SHADOW_REG_ENx=1, both registers that
0043 control the duty cycle for channel x have a second "shadow"/buffer reg synthesised.
0044 At runtime a bit wide register exposed to APB can be used to toggle on/off
0045 synchronised mode for all channels it has been synthesised for.
0046 Each bit of "microchip,sync-update-mask" corresponds to a PWM channel & represents
0047 whether synchronous mode is possible for the PWM channel.
0048
0049 $ref: /schemas/types.yaml#/definitions/uint32
0050 default: 0
0051
0052 microchip,dac-mode-mask:
0053 description: |
0054 Optional, per-channel Low Ripple DAC mode is possible on this IP core. It creates
0055 a minimum period pulse train whose High/Low average is that of the chosen duty
0056 cycle. This "DAC" will have far better bandwidth and ripple performance than the
0057 standard PWM algorithm can achieve. A 16 bit DAC_MODE module parameter of the IP
0058 core, set at instantiation and by the bitstream programmed to the FPGA, determines
0059 whether a given channel operates in regular PWM or DAC mode.
0060 Each bit corresponds to a PWM channel & represents whether DAC mode is enabled
0061 for that channel.
0062
0063 $ref: /schemas/types.yaml#/definitions/uint32
0064 default: 0
0065
0066 required:
0067 - compatible
0068 - reg
0069 - clocks
0070
0071 additionalProperties: false
0072
0073 examples:
0074 - |
0075 pwm@41000000 {
0076 compatible = "microchip,corepwm-rtl-v4";
0077 microchip,sync-update-mask = /bits/ 32 <0>;
0078 clocks = <&clkcfg 30>;
0079 reg = <0x41000000 0xF0>;
0080 #pwm-cells = <2>;
0081 };
