0001 Freescale Peripheral Management Access Unit (PAMU) Device Tree Binding
0002
0003 DESCRIPTION
0004
0005 The PAMU is an I/O MMU that provides device-to-memory access control and
0006 address translation capabilities.
0007
0008 Required properties:
0009
0010 - compatible : <string>
0011 First entry is a version-specific string, such as
0012 "fsl,pamu-v1.0". The second is "fsl,pamu".
0013 - ranges : <prop-encoded-array>
0014 A standard property. Utilized to describe the memory mapped
0015 I/O space utilized by the controller. The size should
0016 be set to the total size of the register space of all
0017 physically present PAMU controllers. For example, for
0018 PAMU v1.0, on an SOC that has five PAMU devices, the size
0019 is 0x5000.
0020 - interrupts : <prop-encoded-array>
0021 Interrupt mappings. The first tuple is the normal PAMU
0022 interrupt, used for reporting access violations. The second
0023 is for PAMU hardware errors, such as PAMU operation errors
0024 and ECC errors.
0025 - #address-cells: <u32>
0026 A standard property.
0027 - #size-cells : <u32>
0028 A standard property.
0029
0030 Optional properties:
0031 - reg : <prop-encoded-array>
0032 A standard property. It represents the CCSR registers of
0033 all child PAMUs combined. Include it to provide support
0034 for legacy drivers.
0035 - fsl,portid-mapping : <u32>
0036 The Coherency Subdomain ID Port Mapping Registers and
0037 Snoop ID Port Mapping registers, which are part of the
0038 CoreNet Coherency fabric (CCF), provide a CoreNet
0039 Coherency Subdomain ID/CoreNet Snoop ID to pamu mapping
0040 functions. Certain bits from these registers should be
0041 set if PAMUs should be snooped. This property defines
0042 a bitmask which selects the bits that should be set if
0043 PAMUs should be snooped.
0044
0045 Child nodes:
0046
0047 Each child node represents one PAMU controller. Each SOC device that is
0048 connected to a specific PAMU device should have a "fsl,pamu-phandle" property
0049 that links to the corresponding specific child PAMU controller.
0050
0051 - reg : <prop-encoded-array>
0052 A standard property. Specifies the physical address and
0053 length (relative to the parent 'ranges' property) of this
0054 PAMU controller's configuration registers. The size should
0055 be set to the size of this PAMU controllers's register space.
0056 For PAMU v1.0, this size is 0x1000.
0057 - fsl,primary-cache-geometry
0058 : <prop-encoded-array>
0059 Two cells that specify the geometry of the primary PAMU
0060 cache. The first is the number of cache lines, and the
0061 second is the number of "ways". For direct-mapped caches,
0062 specify a value of 1.
0063 - fsl,secondary-cache-geometry
0064 : <prop-encoded-array>
0065 Two cells that specify the geometry of the secondary PAMU
0066 cache. The first is the number of cache lines, and the
0067 second is the number of "ways". For direct-mapped caches,
0068 specify a value of 1.
0069
0070 Device nodes:
0071
0072 Devices that have LIODNs need to specify links to the parent PAMU controller
0073 (the actual PAMU controller that this device is connected to) and a pointer to
0074 the LIODN register, if applicable.
0075
0076 - fsl,iommu-parent
0077 : <phandle>
0078 Phandle to the single, specific PAMU controller node to which
0079 this device is connect. The PAMU topology is represented in
0080 the device tree to assist code that dynamically determines the
0081 best LIODN values to minimize PAMU cache thrashing.
0082
0083 - fsl,liodn-reg : <prop-encoded-array>
0084 Two cells that specify the location of the LIODN register
0085 for this device. Required for devices that have a single
0086 LIODN. The first cell is a phandle to a node that contains
0087 the registers where the LIODN is to be set. The second is
0088 the offset from the first "reg" resource of the node where
0089 the specific LIODN register is located.
0090
0091
0092 Example:
0093
0094 iommu@20000 {
0095 compatible = "fsl,pamu-v1.0", "fsl,pamu";
0096 reg = <0x20000 0x5000>;
0097 ranges = <0 0x20000 0x5000>;
0098 fsl,portid-mapping = <0xf80000>;
0099 #address-cells = <1>;
0100 #size-cells = <1>;
0101 interrupts = <
0102 24 2 0 0
0103 16 2 1 30>;
0104
0105 pamu0: pamu@0 {
0106 reg = <0 0x1000>;
0107 fsl,primary-cache-geometry = <32 1>;
0108 fsl,secondary-cache-geometry = <128 2>;
0109 };
0110
0111 pamu1: pamu@1000 {
0112 reg = <0x1000 0x1000>;
0113 fsl,primary-cache-geometry = <32 1>;
0114 fsl,secondary-cache-geometry = <128 2>;
0115 };
0116
0117 pamu2: pamu@2000 {
0118 reg = <0x2000 0x1000>;
0119 fsl,primary-cache-geometry = <32 1>;
0120 fsl,secondary-cache-geometry = <128 2>;
0121 };
0122
0123 pamu3: pamu@3000 {
0124 reg = <0x3000 0x1000>;
0125 fsl,primary-cache-geometry = <32 1>;
0126 fsl,secondary-cache-geometry = <128 2>;
0127 };
0128
0129 pamu4: pamu@4000 {
0130 reg = <0x4000 0x1000>;
0131 fsl,primary-cache-geometry = <32 1>;
0132 fsl,secondary-cache-geometry = <128 2>;
0133 };
0134 };
0135
0136 guts: global-utilities@e0000 {
0137 compatible = "fsl,qoriq-device-config-1.0";
0138 reg = <0xe0000 0xe00>;
0139 fsl,has-rstcr;
0140 #sleep-cells = <1>;
0141 fsl,liodn-bits = <12>;
0142 };
0143
0144 /include/ "qoriq-dma-0.dtsi"
0145 dma@100300 {
0146 fsl,iommu-parent = <&pamu0>;
0147 fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
0148 };
