0001 * Freescale MSI interrupt controller
0002
0003 Required properties:
0004 - compatible : compatible list, may contain one or two entries
0005 The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
0006 etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
0007 "fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
0008 version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
0009 provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
0010 should be used. The first entry is optional; the second entry is
0011 required.
0012
0013 - reg : It may contain one or two regions. The first region should contain
0014 the address and the length of the shared message interrupt register set.
0015 The second region should contain the address of aliased MSIIR or MSIIR1
0016 register for platforms that have such an alias, if using MSIIR1, the second
0017 region must be added because different MSI group has different MSIIR1 offset.
0018
0019 - interrupts : each one of the interrupts here is one entry per 32 MSIs,
0020 and routed to the host interrupt controller. the interrupts should
0021 be set as edge sensitive. If msi-available-ranges is present, only
0022 the interrupts that correspond to available ranges shall be present.
0023
0024 Optional properties:
0025 - msi-available-ranges: use <start count> style section to define which
0026 msi interrupt can be used in the 256 msi interrupts. This property is
0027 optional, without this, all the MSI interrupts can be used.
0028 Each available range must begin and end on a multiple of 32 (i.e.
0029 no splitting an individual MSI register or the associated PIC interrupt).
0030 MPIC v4.3 does not support this property because the 32 interrupts of an
0031 individual register are not continuous when using MSIIR1.
0032
0033 - msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
0034 is used for MSI messaging. The address of MSIIR in PCI address space is
0035 the MSI message address.
0036
0037 This property may be used in virtualized environments where the hypervisor
0038 has created an alternate mapping for the MSIR block. See below for an
0039 explanation.
0040
0041
0042 Example:
0043 msi@41600 {
0044 compatible = "fsl,mpc8610-msi", "fsl,mpic-msi";
0045 reg = <0x41600 0x80>;
0046 msi-available-ranges = <0 0x100>;
0047 interrupts = <
0048 0xe0 0
0049 0xe1 0
0050 0xe2 0
0051 0xe3 0
0052 0xe4 0
0053 0xe5 0
0054 0xe6 0
0055 0xe7 0>;
0056 interrupt-parent = <&mpic>;
0057 };
0058
0059 msi@41600 {
0060 compatible = "fsl,mpic-msi-v4.3";
0061 reg = <0x41600 0x200 0x44148 4>;
0062 interrupts = <
0063 0xe0 0 0 0
0064 0xe1 0 0 0
0065 0xe2 0 0 0
0066 0xe3 0 0 0
0067 0xe4 0 0 0
0068 0xe5 0 0 0
0069 0xe6 0 0 0
0070 0xe7 0 0 0
0071 0x100 0 0 0
0072 0x101 0 0 0
0073 0x102 0 0 0
0074 0x103 0 0 0
0075 0x104 0 0 0
0076 0x105 0 0 0
0077 0x106 0 0 0
0078 0x107 0 0 0>;
0079 };
0080
0081 The Freescale hypervisor and msi-address-64
0082 -------------------------------------------
0083 Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
0084 Freescale MSI driver calculates the address of MSIIR (in the MSI register
0085 block) and sets that address as the MSI message address.
0086
0087 In a virtualized environment, the hypervisor may need to create an IOMMU
0088 mapping for MSIIR. The Freescale ePAPR hypervisor has this requirement
0089 because of hardware limitations of the Peripheral Access Management Unit
0090 (PAMU), which is currently the only IOMMU that the hypervisor supports.
0091 The ATMU is programmed with the guest physical address, and the PAMU
0092 intercepts transactions and reroutes them to the true physical address.
0093
0094 In the PAMU, each PCI controller is given only one primary window. The
0095 PAMU restricts DMA operations so that they can only occur within a window.
0096 Because PCI devices must be able to DMA to memory, the primary window must
0097 be used to cover all of the guest's memory space.
0098
0099 PAMU primary windows can be divided into 256 subwindows, and each
0100 subwindow can have its own address mapping ("guest physical" to "true
0101 physical"). However, each subwindow has to have the same alignment, which
0102 means they cannot be located at just any address. Because of these
0103 restrictions, it is usually impossible to create a 4KB subwindow that
0104 covers MSIIR where it's normally located.
0105
0106 Therefore, the hypervisor has to create a subwindow inside the same
0107 primary window used for memory, but mapped to the MSIR block (where MSIIR
0108 lives). The first subwindow after the end of guest memory is used for
0109 this. The address specified in the msi-address-64 property is the PCI
0110 address of MSIIR. The hypervisor configures the PAMU to map that address to
0111 the true physical address of MSIIR.
