0001 =====================================================================
0002 Freescale MPIC Interrupt Controller Node
0003 Copyright (C) 2010,2011 Freescale Semiconductor Inc.
0004 =====================================================================
0005
0006 The Freescale MPIC interrupt controller is found on all PowerQUICC
0007 and QorIQ processors and is compatible with the Open PIC. The
0008 notable difference from Open PIC binding is the addition of 2
0009 additional cells in the interrupt specifier defining interrupt type
0010 information.
0011
0012 PROPERTIES
0013
0014 - compatible
0015 Usage: required
0016 Value type: <string>
0017 Definition: Shall include "fsl,mpic". Freescale MPIC
0018 controllers compatible with this binding have Block
0019 Revision Registers BRR1 and BRR2 at offset 0x0 and
0020 0x10 in the MPIC.
0021
0022 - reg
0023 Usage: required
0024 Value type: <prop-encoded-array>
0025 Definition: A standard property. Specifies the physical
0026 offset and length of the device's registers within the
0027 CCSR address space.
0028
0029 - interrupt-controller
0030 Usage: required
0031 Value type: <empty>
0032 Definition: Specifies that this node is an interrupt
0033 controller
0034
0035 - #interrupt-cells
0036 Usage: required
0037 Value type: <u32>
0038 Definition: Shall be 2 or 4. A value of 2 means that interrupt
0039 specifiers do not contain the interrupt-type or type-specific
0040 information cells.
0041
0042 - #address-cells
0043 Usage: required
0044 Value type: <u32>
0045 Definition: Shall be 0.
0046
0047 - pic-no-reset
0048 Usage: optional
0049 Value type: <empty>
0050 Definition: The presence of this property specifies that the
0051 MPIC must not be reset by the client program, and that
0052 the boot program has initialized all interrupt source
0053 configuration registers to a sane state-- masked or
0054 directed at other cores. This ensures that the client
0055 program will not receive interrupts for sources not belonging
0056 to the client. The presence of this property also mandates
0057 that any initialization related to interrupt sources shall
0058 be limited to sources explicitly referenced in the device tree.
0059
0060 - big-endian
0061 Usage: optional
0062 Value type: <empty>
0063 If present the MPIC will be assumed to be big-endian. Some
0064 device-trees omit this property on MPIC nodes even when the MPIC is
0065 in fact big-endian, so certain boards override this property.
0066
0067 - single-cpu-affinity
0068 Usage: optional
0069 Value type: <empty>
0070 If present the MPIC will be assumed to only be able to route
0071 non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC).
0072
0073 - last-interrupt-source
0074 Usage: optional
0075 Value type: <u32>
0076 Some MPICs do not correctly report the number of hardware sources
0077 in the global feature registers. If specified, this field will
0078 override the value read from MPIC_GREG_FEATURE_LAST_SRC.
0079
0080 INTERRUPT SPECIFIER DEFINITION
0081
0082 Interrupt specifiers consists of 4 cells encoded as
0083 follows:
0084
0085 <1st-cell> interrupt-number
0086
0087 Identifies the interrupt source. The meaning
0088 depends on the type of interrupt.
0089
0090 Note: If the interrupt-type cell is undefined
0091 (i.e. #interrupt-cells = 2), this cell
0092 should be interpreted the same as for
0093 interrupt-type 0-- i.e. an external or
0094 normal SoC device interrupt.
0095
0096 <2nd-cell> level-sense information, encoded as follows:
0097 0 = low-to-high edge triggered
0098 1 = active low level-sensitive
0099 2 = active high level-sensitive
0100 3 = high-to-low edge triggered
0101
0102 <3rd-cell> interrupt-type
0103
0104 The following types are supported:
0105
0106 0 = external or normal SoC device interrupt
0107
0108 The interrupt-number cell contains
0109 the SoC device interrupt number. The
0110 type-specific cell is undefined. The
0111 interrupt-number is derived from the
0112 MPIC a block of registers referred to as
0113 the "Interrupt Source Configuration Registers".
0114 Each source has 32-bytes of registers
0115 (vector/priority and destination) in this
0116 region. So interrupt 0 is at offset 0x0,
0117 interrupt 1 is at offset 0x20, and so on.
0118
0119 1 = error interrupt
0120
0121 The interrupt-number cell contains
0122 the SoC device interrupt number for
0123 the error interrupt. The type-specific
0124 cell identifies the specific error
0125 interrupt number.
0126
0127 2 = MPIC inter-processor interrupt (IPI)
0128
0129 The interrupt-number cell identifies
0130 the MPIC IPI number. The type-specific
0131 cell is undefined.
0132
0133 3 = MPIC timer interrupt
0134
0135 The interrupt-number cell identifies
0136 the MPIC timer number. The type-specific
0137 cell is undefined.
0138
0139 <4th-cell> type-specific information
0140
0141 The type-specific cell is encoded as follows:
0142
0143 - For interrupt-type 1 (error interrupt),
0144 the type-specific cell contains the
0145 bit number of the error interrupt in the
0146 Error Interrupt Summary Register.
0147
0148 EXAMPLE 1
0149 /*
0150 * mpic interrupt controller with 4 cells per specifier
0151 */
0152 mpic: pic@40000 {
0153 compatible = "fsl,mpic";
0154 interrupt-controller;
0155 #interrupt-cells = <4>;
0156 #address-cells = <0>;
0157 reg = <0x40000 0x40000>;
0158 };
0159
0160 EXAMPLE 2
0161 /*
0162 * The MPC8544 I2C controller node has an internal
0163 * interrupt number of 27. As per the reference manual
0164 * this corresponds to interrupt source configuration
0165 * registers at 0x5_0560.
0166 *
0167 * The interrupt source configuration registers begin
0168 * at 0x5_0000.
0169 *
0170 * To compute the interrupt specifier interrupt number
0171 *
0172 * 0x560 >> 5 = 43
0173 *
0174 * The interrupt source configuration registers begin
0175 * at 0x5_0000, and so the i2c vector/priority registers
0176 * are at 0x5_0560.
0177 */
0178 i2c@3000 {
0179 #address-cells = <1>;
0180 #size-cells = <0>;
0181 cell-index = <0>;
0182 compatible = "fsl-i2c";
0183 reg = <0x3000 0x100>;
0184 interrupts = <43 2>;
0185 interrupt-parent = <&mpic>;
0186 dfsrr;
0187 };
0188
0189
0190 EXAMPLE 3
0191 /*
0192 * Definition of a node defining the 4
0193 * MPIC IPI interrupts. Note the interrupt
0194 * type of 2.
0195 */
0196 ipi@410a0 {
0197 compatible = "fsl,mpic-ipi";
0198 reg = <0x40040 0x10>;
0199 interrupts = <0 0 2 0
0200 1 0 2 0
0201 2 0 2 0
0202 3 0 2 0>;
0203 };
0204
0205 EXAMPLE 4
0206 /*
0207 * Definition of a node defining the MPIC
0208 * global timers. Note the interrupt
0209 * type of 3.
0210 */
0211 timer0: timer@41100 {
0212 compatible = "fsl,mpic-global-timer";
0213 reg = <0x41100 0x100 0x41300 4>;
0214 interrupts = <0 0 3 0
0215 1 0 3 0
0216 2 0 3 0
0217 3 0 3 0>;
0218 };
0219
0220 EXAMPLE 5
0221 /*
0222 * Definition of an error interrupt (interrupt type 1).
0223 * SoC interrupt number is 16 and the specific error
0224 * interrupt bit in the error interrupt summary register
0225 * is 23.
0226 */
0227 memory-controller@8000 {
0228 compatible = "fsl,p4080-memory-controller";
0229 reg = <0x8000 0x1000>;
0230 interrupts = <16 2 1 23>;
0231 };
