0001 * Freescale MPIC timers
0002
0003 Required properties:
0004 - compatible: "fsl,mpic-global-timer"
0005
0006 - reg : Contains two regions. The first is the main timer register bank
0007 (GTCCRxx, GTBCRxx, GTVPRxx, GTDRxx). The second is the timer control
0008 register (TCRx) for the group.
0009
0010 - fsl,available-ranges: use <start count> style section to define which
0011 timer interrupts can be used. This property is optional; without this,
0012 all timers within the group can be used.
0013
0014 - interrupts: one interrupt per timer in the group, in order, starting
0015 with timer zero. If timer-available-ranges is present, only the
0016 interrupts that correspond to available timers shall be present.
0017
0018 Example:
0019 /* Note that this requires #interrupt-cells to be 4 */
0020 timer0: timer@41100 {
0021 compatible = "fsl,mpic-global-timer";
0022 reg = <0x41100 0x100 0x41300 4>;
0023
0024 /* Another AMP partition is using timers 0 and 1 */
0025 fsl,available-ranges = <2 2>;
0026
0027 interrupts = <2 0 3 0
0028 3 0 3 0>;
0029 };
0030
0031 timer1: timer@42100 {
0032 compatible = "fsl,mpic-global-timer";
0033 reg = <0x42100 0x100 0x42300 4>;
0034 interrupts = <4 0 3 0
0035 5 0 3 0
0036 6 0 3 0
0037 7 0 3 0>;
0038 };
