0001 * FSL MPIC Message Registers
0002
0003 This binding specifies what properties must be available in the device tree
0004 representation of the message register blocks found in some FSL MPIC
0005 implementations.
0006
0007 Required properties:
0008
0009 - compatible: Specifies the compatibility list for the message register
0010 block. The type shall be <string-list> and the value shall be of the form
0011 "fsl,mpic-v<version>-msgr", where <version> is the version number of
0012 the MPIC containing the message registers.
0013
0014 - reg: Specifies the base physical address(s) and size(s) of the
0015 message register block's addressable register space. The type shall be
0016 <prop-encoded-array>.
0017
0018 - interrupts: Specifies a list of interrupt-specifiers which are available
0019 for receiving interrupts. Interrupt-specifier consists of two cells: first
0020 cell is interrupt-number and second cell is level-sense. The type shall be
0021 <prop-encoded-array>.
0022
0023 Optional properties:
0024
0025 - mpic-msgr-receive-mask: Specifies what registers in the containing block
0026 are allowed to receive interrupts. The value is a bit mask where a set
0027 bit at bit 'n' indicates that message register 'n' can receive interrupts.
0028 Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall
0029 be <u32>. If not present, then all of the message registers in the block
0030 are available.
0031
0032 Aliases:
0033
0034 An alias should be created for every message register block. They are not
0035 required, though. However, a particular implementation of this binding
0036 may require aliases to be present. Aliases are of the form
0037 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number.
0038 Numbers shall start at 0.
0039
0040 Example:
0041
0042 aliases {
0043 mpic-msgr-block0 = &mpic_msgr_block0;
0044 mpic-msgr-block1 = &mpic_msgr_block1;
0045 };
0046
0047 mpic_msgr_block0: mpic-msgr-block@41400 {
0048 compatible = "fsl,mpic-v3.1-msgr";
0049 reg = <0x41400 0x200>;
0050 // Message registers 0 and 2 in this block can receive interrupts on
0051 // sources 0xb0 and 0xb2, respectively.
0052 interrupts = <0xb0 2 0xb2 2>;
0053 mpic-msgr-receive-mask = <0x5>;
0054 };
0055
0056 mpic_msgr_block1: mpic-msgr-block@42400 {
0057 compatible = "fsl,mpic-v3.1-msgr";
0058 reg = <0x42400 0x200>;
0059 // Message registers 0 and 2 in this block can receive interrupts on
0060 // sources 0xb4 and 0xb6, respectively.
0061 interrupts = <0xb4 2 0xb6 2>;
0062 mpic-msgr-receive-mask = <0x5>;
0063 };
