0001 MPC5200 Device Tree Bindings
0002 ----------------------------
0003
0004 (c) 2006-2009 Secret Lab Technologies Ltd
0005 Grant Likely <grant.likely@secretlab.ca>
0006
0007 Naming conventions
0008 ------------------
0009 For mpc5200 on-chip devices, the format for each compatible value is
0010 <chip>-<device>[-<mode>]. The OS should be able to match a device driver
0011 to the device based solely on the compatible value. If two drivers
0012 match on the compatible list; the 'most compatible' driver should be
0013 selected.
0014
0015 The split between the MPC5200 and the MPC5200B leaves a bit of a
0016 conundrum. How should the compatible property be set up to provide
0017 maximum compatibility information; but still accurately describe the
0018 chip? For the MPC5200; the answer is easy. Most of the SoC devices
0019 originally appeared on the MPC5200. Since they didn't exist anywhere
0020 else; the 5200 compatible properties will contain only one item;
0021 "fsl,mpc5200-<device>".
0022
0023 The 5200B is almost the same as the 5200, but not quite. It fixes
0024 silicon bugs and it adds a small number of enhancements. Most of the
0025 devices either provide exactly the same interface as on the 5200. A few
0026 devices have extra functions but still have a backwards compatible mode.
0027 To express this information as completely as possible, 5200B device trees
0028 should have two items in the compatible list:
0029 compatible = "fsl,mpc5200b-<device>","fsl,mpc5200-<device>";
0030
0031 It is *strongly* recommended that 5200B device trees follow this convention
0032 (instead of only listing the base mpc5200 item).
0033
0034 ie. ethernet on mpc5200: compatible = "fsl,mpc5200-fec";
0035 ethernet on mpc5200b: compatible = "fsl,mpc5200b-fec", "fsl,mpc5200-fec";
0036
0037 Modal devices, like PSCs, also append the configured function to the
0038 end of the compatible field. ie. A PSC in i2s mode would specify
0039 "fsl,mpc5200-psc-i2s", not "fsl,mpc5200-i2s". This convention is chosen to
0040 avoid naming conflicts with non-psc devices providing the same
0041 function. For example, "fsl,mpc5200-spi" and "fsl,mpc5200-psc-spi" describe
0042 the mpc5200 simple spi device and a PSC spi mode respectively.
0043
0044 At the time of writing, exact chip may be either 'fsl,mpc5200' or
0045 'fsl,mpc5200b'.
0046
0047 The soc node
0048 ------------
0049 This node describes the on chip SOC peripherals. Every mpc5200 based
0050 board will have this node, and as such there is a common naming
0051 convention for SOC devices.
0052
0053 Required properties:
0054 name description
0055 ---- -----------
0056 ranges Memory range of the internal memory mapped registers.
0057 Should be <0 [baseaddr] 0xc000>
0058 reg Should be <[baseaddr] 0x100>
0059 compatible mpc5200: "fsl,mpc5200-immr"
0060 mpc5200b: "fsl,mpc5200b-immr"
0061 system-frequency 'fsystem' frequency in Hz; XLB, IPB, USB and PCI
0062 clocks are derived from the fsystem clock.
0063 bus-frequency IPB bus frequency in Hz. Clock rate
0064 used by most of the soc devices.
0065
0066 soc child nodes
0067 ---------------
0068 Any on chip SOC devices available to Linux must appear as soc5200 child nodes.
0069
0070 Note: The tables below show the value for the mpc5200. A mpc5200b device
0071 tree should use the "fsl,mpc5200b-<device>","fsl,mpc5200-<device>" form.
0072
0073 Required soc5200 child nodes:
0074 name compatible Description
0075 ---- ---------- -----------
0076 cdm@<addr> fsl,mpc5200-cdm Clock Distribution
0077 interrupt-controller@<addr> fsl,mpc5200-pic need an interrupt
0078 controller to boot
0079 bestcomm@<addr> fsl,mpc5200-bestcomm Bestcomm DMA controller
0080
0081 Recommended soc5200 child nodes; populate as needed for your board
0082 name compatible Description
0083 ---- ---------- -----------
0084 timer@<addr> fsl,mpc5200-gpt General purpose timers
0085 gpio@<addr> fsl,mpc5200-gpio MPC5200 simple gpio controller
0086 gpio@<addr> fsl,mpc5200-gpio-wkup MPC5200 wakeup gpio controller
0087 rtc@<addr> fsl,mpc5200-rtc Real time clock
0088 mscan@<addr> fsl,mpc5200-mscan CAN bus controller
0089 pci@<addr> fsl,mpc5200-pci PCI bridge
0090 serial@<addr> fsl,mpc5200-psc-uart PSC in serial mode
0091 i2s@<addr> fsl,mpc5200-psc-i2s PSC in i2s mode
0092 ac97@<addr> fsl,mpc5200-psc-ac97 PSC in ac97 mode
0093 spi@<addr> fsl,mpc5200-psc-spi PSC in spi mode
0094 irda@<addr> fsl,mpc5200-psc-irda PSC in IrDA mode
0095 spi@<addr> fsl,mpc5200-spi MPC5200 spi device
0096 ethernet@<addr> fsl,mpc5200-fec MPC5200 ethernet device
0097 ata@<addr> fsl,mpc5200-ata IDE ATA interface
0098 i2c@<addr> fsl,mpc5200-i2c I2C controller
0099 usb@<addr> fsl,mpc5200-ohci,ohci-be USB controller
0100 xlb@<addr> fsl,mpc5200-xlb XLB arbitrator
0101
0102 fsl,mpc5200-gpt nodes
0103 ---------------------
0104 On the mpc5200 and 5200b, GPT0 has a watchdog timer function. If the board
0105 design supports the internal wdt, then the device node for GPT0 should
0106 include the empty property 'fsl,has-wdt'. Note that this does not activate
0107 the watchdog. The timer will function as a GPT if the timer api is used, and
0108 it will function as watchdog if the watchdog device is used. The watchdog
0109 mode has priority over the gpt mode, i.e. if the watchdog is activated, any
0110 gpt api call to this timer will fail with -EBUSY.
0111
0112 If you add the property
0113 fsl,wdt-on-boot = <n>;
0114 GPT0 will be marked as in-use watchdog, i.e. blocking every gpt access to it.
0115 If n>0, the watchdog is started with a timeout of n seconds. If n=0, the
0116 configuration of the watchdog is not touched. This is useful in two cases:
0117 - just mark GPT0 as watchdog, blocking gpt accesses, and configure it later;
0118 - do not touch a configuration assigned by the boot loader which supervises
0119 the boot process itself.
0120
0121 The watchdog will respect the CONFIG_WATCHDOG_NOWAYOUT option.
0122
0123 An mpc5200-gpt can be used as a single line GPIO controller. To do so,
0124 add the following properties to the gpt node:
0125 gpio-controller;
0126 #gpio-cells = <2>;
0127 When referencing the GPIO line from another node, the first cell must always
0128 be zero and the second cell represents the gpio flags and described in the
0129 gpio device tree binding.
0130
0131 An mpc5200-gpt can be used as a single line edge sensitive interrupt
0132 controller. To do so, add the following properties to the gpt node:
0133 interrupt-controller;
0134 #interrupt-cells = <1>;
0135 When referencing the IRQ line from another node, the cell represents the
0136 sense mode; 1 for edge rising, 2 for edge falling.
0137
0138 fsl,mpc5200-psc nodes
0139 ---------------------
0140 The PSCs should include a cell-index which is the index of the PSC in
0141 hardware. cell-index is used to determine which shared SoC registers to
0142 use when setting up PSC clocking. cell-index number starts at '0'. ie:
0143 PSC1 has 'cell-index = <0>'
0144 PSC4 has 'cell-index = <3>'
0145
0146 PSC in i2s mode: The mpc5200 and mpc5200b PSCs are not compatible when in
0147 i2s mode. An 'mpc5200b-psc-i2s' node cannot include 'mpc5200-psc-i2s' in the
0148 compatible field.
0149
0150
0151 fsl,mpc5200-gpio and fsl,mpc5200-gpio-wkup nodes
0152 ------------------------------------------------
0153 Each GPIO controller node should have the empty property gpio-controller and
0154 #gpio-cells set to 2. First cell is the GPIO number which is interpreted
0155 according to the bit numbers in the GPIO control registers. The second cell
0156 is for flags which is currently unused.
0157
0158 fsl,mpc5200-fec nodes
0159 ---------------------
0160 The FEC node can specify one of the following properties to configure
0161 the MII link:
0162 - fsl,7-wire-mode - An empty property that specifies the link uses 7-wire
0163 mode instead of MII
0164 - current-speed - Specifies that the MII should be configured for a fixed
0165 speed. This property should contain two cells. The
0166 first cell specifies the speed in Mbps and the second
0167 should be '0' for half duplex and '1' for full duplex
0168 - phy-handle - Contains a phandle to an Ethernet PHY.
0169
0170 Interrupt controller (fsl,mpc5200-pic) node
0171 -------------------------------------------
0172 The mpc5200 pic binding splits hardware IRQ numbers into two levels. The
0173 split reflects the layout of the PIC hardware itself, which groups
0174 interrupts into one of three groups; CRIT, MAIN or PERP. Also, the
0175 Bestcomm dma engine has its own set of interrupt sources which are
0176 cascaded off of peripheral interrupt 0, which the driver interprets as a
0177 fourth group, SDMA.
0178
0179 The interrupts property for device nodes using the mpc5200 pic consists
0180 of three cells; <L1 L2 level>
0181
0182 L1 := [CRIT=0, MAIN=1, PERP=2, SDMA=3]
0183 L2 := interrupt number; directly mapped from the value in the
0184 "ICTL PerStat, MainStat, CritStat Encoded Register"
0185 level := [LEVEL_HIGH=0, EDGE_RISING=1, EDGE_FALLING=2, LEVEL_LOW=3]
0186
0187 For external IRQs, use the following interrupt property values (how to
0188 specify external interrupts is a frequently asked question):
0189 External interrupts:
0190 external irq0: interrupts = <0 0 n>;
0191 external irq1: interrupts = <1 1 n>;
0192 external irq2: interrupts = <1 2 n>;
0193 external irq3: interrupts = <1 3 n>;
0194 'n' is sense (0: level high, 1: edge rising, 2: edge falling 3: level low)
0195
0196 fsl,mpc5200-mscan nodes
0197 -----------------------
0198 See file Documentation/devicetree/bindings/powerpc/fsl/mpc5200.txt
