0001 MPC5121 PSC Device Tree Bindings
0002
0003 PSC in UART mode
0004 ----------------
0005
0006 For PSC in UART mode the needed PSC serial devices
0007 are specified by fsl,mpc5121-psc-uart nodes in the
0008 fsl,mpc5121-immr SoC node. Additionally the PSC FIFO
0009 Controller node fsl,mpc5121-psc-fifo is required there:
0010
0011 fsl,mpc512x-psc-uart nodes
0012 --------------------------
0013
0014 Required properties :
0015 - compatible : Should contain "fsl,<soc>-psc-uart" and "fsl,<soc>-psc"
0016 Supported <soc>s: mpc5121, mpc5125
0017 - reg : Offset and length of the register set for the PSC device
0018 - interrupts : <a b> where a is the interrupt number of the
0019 PSC FIFO Controller and b is a field that represents an
0020 encoding of the sense and level information for the interrupt.
0021
0022 Recommended properties :
0023 - fsl,rx-fifo-size : the size of the RX fifo slice (a multiple of 4)
0024 - fsl,tx-fifo-size : the size of the TX fifo slice (a multiple of 4)
0025
0026 PSC in SPI mode
0027 ---------------
0028
0029 Similar to the UART mode a PSC can be operated in SPI mode. The compatible used
0030 for that is fsl,mpc5121-psc-spi. It requires a fsl,mpc5121-psc-fifo as well.
0031 The required and recommended properties are identical to the
0032 fsl,mpc5121-psc-uart nodes, just use spi instead of uart in the compatible
0033 string.
0034
0035 fsl,mpc512x-psc-fifo node
0036 -------------------------
0037
0038 Required properties :
0039 - compatible : Should be "fsl,<soc>-psc-fifo"
0040 Supported <soc>s: mpc5121, mpc5125
0041 - reg : Offset and length of the register set for the PSC
0042 FIFO Controller
0043 - interrupts : <a b> where a is the interrupt number of the
0044 PSC FIFO Controller and b is a field that represents an
0045 encoding of the sense and level information for the interrupt.
0046
0047 Recommended properties :
0048 - clocks : specifies the clock needed to operate the fifo controller
0049 - clock-names : name(s) for the clock(s) listed in clocks
0050
0051 Example for a board using PSC0 and PSC1 devices in serial mode:
0052
0053 serial@11000 {
0054 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
0055 cell-index = <0>;
0056 reg = <0x11000 0x100>;
0057 interrupts = <40 0x8>;
0058 interrupt-parent = < &ipic >;
0059 fsl,rx-fifo-size = <16>;
0060 fsl,tx-fifo-size = <16>;
0061 };
0062
0063 serial@11100 {
0064 compatible = "fsl,mpc5121-psc-uart", "fsl,mpc5121-psc";
0065 cell-index = <1>;
0066 reg = <0x11100 0x100>;
0067 interrupts = <40 0x8>;
0068 interrupt-parent = < &ipic >;
0069 fsl,rx-fifo-size = <16>;
0070 fsl,tx-fifo-size = <16>;
0071 };
0072
0073 pscfifo@11f00 {
0074 compatible = "fsl,mpc5121-psc-fifo";
0075 reg = <0x11f00 0x100>;
0076 interrupts = <40 0x8>;
0077 interrupt-parent = < &ipic >;
0078 };
