0001 ===================================================================
0002 Debug Control and Status Register (DCSR) Binding
0003 Copyright 2011 Freescale Semiconductor Inc.
0004
0005 NOTE: The bindings described in this document are preliminary and subject
0006 to change. Some of the compatible strings that contain only generic names
0007 may turn out to be inappropriate, or need additional properties to describe
0008 the integration of the block with the rest of the chip.
0009
0010 =====================================================================
0011 Debug Control and Status Register Memory Map
0012
0013 Description
0014
0015 This node defines the base address and range for the
0016 defined DCSR Memory Map. Child nodes will describe the individual
0017 debug blocks defined within this memory space.
0018
0019 PROPERTIES
0020
0021 - compatible
0022 Usage: required
0023 Value type: <string>
0024 Definition: Must include "fsl,dcsr" and "simple-bus".
0025 The DCSR space exists in the memory-mapped bus.
0026
0027 - #address-cells
0028 Usage: required
0029 Value type: <u32>
0030 Definition: A standard property. Defines the number of cells
0031 or representing physical addresses in child nodes.
0032
0033 - #size-cells
0034 Usage: required
0035 Value type: <u32>
0036 Definition: A standard property. Defines the number of cells
0037 or representing the size of physical addresses in
0038 child nodes.
0039
0040 - ranges
0041 Usage: required
0042 Value type: <prop-encoded-array>
0043 Definition: A standard property. Specifies the physical address
0044 range of the DCSR space.
0045
0046 EXAMPLE
0047 dcsr: dcsr@f00000000 {
0048 #address-cells = <1>;
0049 #size-cells = <1>;
0050 compatible = "fsl,dcsr", "simple-bus";
0051 ranges = <0x00000000 0xf 0x00000000 0x01008000>;
0052 };
0053
0054 =====================================================================
0055 Event Processing Unit
0056
0057 This node represents the region of DCSR space allocated to the EPU
0058
0059 PROPERTIES
0060
0061 - compatible
0062 Usage: required
0063 Value type: <string>
0064 Definition: Must include "fsl,dcsr-epu"
0065
0066 - interrupts
0067 Usage: required
0068 Value type: <prop_encoded-array>
0069 Definition: Specifies the interrupts generated by the EPU.
0070 The value of the interrupts property consists of three
0071 interrupt specifiers. The format of the specifier is defined
0072 by the binding document describing the node's interrupt parent.
0073
0074 The EPU counters can be configured to assert the performance
0075 monitor interrupt signal based on either counter overflow or value
0076 match. Which counter asserted the interrupt is captured in an EPU
0077 Counter Interrupt Status Register (EPCPUISR).
0078
0079 The EPU unit can also be configured to assert either or both of
0080 two interrupt signals based on debug event sources within the SoC.
0081 The interrupt signals are epu_xt_int0 and epu_xt_int1.
0082 Which event source asserted the interrupt is captured in an EPU
0083 Interrupt Status Register (EPISR0,EPISR1).
0084
0085 Interrupt numbers are listed in order (perfmon, event0, event1).
0086
0087 - reg
0088 Usage: required
0089 Value type: <prop-encoded-array>
0090 Definition: A standard property. Specifies the physical address
0091 offset and length of the DCSR space registers of the device
0092 configuration block.
0093
0094 EXAMPLE
0095 dcsr-epu@0 {
0096 compatible = "fsl,dcsr-epu";
0097 interrupts = <52 2 0 0
0098 84 2 0 0
0099 85 2 0 0>;
0100 interrupt-parent = <&mpic>;
0101 reg = <0x0 0x1000>;
0102 };
0103
0104 =======================================================================
0105 Nexus Port Controller
0106
0107 This node represents the region of DCSR space allocated to the NPC
0108
0109 PROPERTIES
0110
0111 - compatible
0112 Usage: required
0113 Value type: <string>
0114 Definition: Must include "fsl,dcsr-npc"
0115
0116 - reg
0117 Usage: required
0118 Value type: <prop-encoded-array>
0119 Definition: A standard property. Specifies the physical address
0120 offset and length of the DCSR space registers of the device
0121 configuration block.
0122 The Nexus Port controller occupies two regions in the DCSR space
0123 with distinct functionality.
0124
0125 The first register range describes the Nexus Port Controller
0126 control and status registers.
0127
0128 The second register range describes the Nexus Port Controller
0129 internal trace buffer. The NPC trace buffer is a small memory buffer
0130 which stages the nexus trace data for transmission via the Aurora port
0131 or to a DDR based trace buffer. In some configurations the NPC trace
0132 buffer can be the only trace buffer used.
0133
0134
0135 EXAMPLE
0136 dcsr-npc {
0137 compatible = "fsl,dcsr-npc";
0138 reg = <0x1000 0x1000 0x1000000 0x8000>;
0139 };
0140
0141 =======================================================================
0142 Nexus Concentrator
0143
0144 This node represents the region of DCSR space allocated to the NXC
0145
0146 PROPERTIES
0147
0148 - compatible
0149 Usage: required
0150 Value type: <string>
0151 Definition: Must include "fsl,dcsr-nxc"
0152
0153 - reg
0154 Usage: required
0155 Value type: <prop-encoded-array>
0156 Definition: A standard property. Specifies the physical address
0157 offset and length of the DCSR space registers of the device
0158 configuration block.
0159
0160 EXAMPLE
0161 dcsr-nxc@2000 {
0162 compatible = "fsl,dcsr-nxc";
0163 reg = <0x2000 0x1000>;
0164 };
0165 =======================================================================
0166 CoreNet Debug Controller
0167
0168 This node represents the region of DCSR space allocated to
0169 the CoreNet Debug controller.
0170
0171 PROPERTIES
0172
0173 - compatible
0174 Usage: required
0175 Value type: <string>
0176 Definition: Must include "fsl,dcsr-corenet"
0177
0178 - reg
0179 Usage: required
0180 Value type: <prop-encoded-array>
0181 Definition: A standard property. Specifies the physical address
0182 offset and length of the DCSR space registers of the device
0183 configuration block.
0184 The CoreNet Debug controller occupies two regions in the DCSR space
0185 with distinct functionality.
0186
0187 The first register range describes the CoreNet Debug Controller
0188 functionalty to perform transaction and transaction attribute matches.
0189
0190 The second register range describes the CoreNet Debug Controller
0191 functionalty to trigger event notifications and debug traces.
0192
0193 EXAMPLE
0194 dcsr-corenet {
0195 compatible = "fsl,dcsr-corenet";
0196 reg = <0x8000 0x1000 0xB0000 0x1000>;
0197 };
0198
0199 =======================================================================
0200 Data Path Debug controller
0201
0202 This node represents the region of DCSR space allocated to
0203 the DPAA Debug Controller. This controller controls debug configuration
0204 for the QMAN and FMAN blocks.
0205
0206 PROPERTIES
0207
0208 - compatible
0209 Usage: required
0210 Value type: <string>
0211 Definition: Must include both an identifier specific to the SoC
0212 or Debug IP of the form "fsl,<soc>-dcsr-dpaa" in addition to the
0213 generic compatible string "fsl,dcsr-dpaa".
0214
0215 - reg
0216 Usage: required
0217 Value type: <prop-encoded-array>
0218 Definition: A standard property. Specifies the physical address
0219 offset and length of the DCSR space registers of the device
0220 configuration block.
0221
0222 EXAMPLE
0223 dcsr-dpaa@9000 {
0224 compatible = "fsl,p4080-dcsr-dpaa", "fsl,dcsr-dpaa";
0225 reg = <0x9000 0x1000>;
0226 };
0227
0228 =======================================================================
0229 OCeaN Debug controller
0230
0231 This node represents the region of DCSR space allocated to
0232 the OCN Debug Controller.
0233
0234 PROPERTIES
0235
0236 - compatible
0237 Usage: required
0238 Value type: <string>
0239 Definition: Must include both an identifier specific to the SoC
0240 or Debug IP of the form "fsl,<soc>-dcsr-ocn" in addition to the
0241 generic compatible string "fsl,dcsr-ocn".
0242
0243 - reg
0244 Usage: required
0245 Value type: <prop-encoded-array>
0246 Definition: A standard property. Specifies the physical address
0247 offset and length of the DCSR space registers of the device
0248 configuration block.
0249
0250 EXAMPLE
0251 dcsr-ocn@11000 {
0252 compatible = "fsl,p4080-dcsr-ocn", "fsl,dcsr-ocn";
0253 reg = <0x11000 0x1000>;
0254 };
0255
0256 =======================================================================
0257 DDR Controller Debug controller
0258
0259 This node represents the region of DCSR space allocated to
0260 the OCN Debug Controller.
0261
0262 PROPERTIES
0263
0264 - compatible
0265 Usage: required
0266 Value type: <string>
0267 Definition: Must include "fsl,dcsr-ddr"
0268
0269 - dev-handle
0270 Usage: required
0271 Definition: A phandle to associate this debug node with its
0272 component controller.
0273
0274 - reg
0275 Usage: required
0276 Value type: <prop-encoded-array>
0277 Definition: A standard property. Specifies the physical address
0278 offset and length of the DCSR space registers of the device
0279 configuration block.
0280
0281 EXAMPLE
0282 dcsr-ddr@12000 {
0283 compatible = "fsl,dcsr-ddr";
0284 dev-handle = <&ddr1>;
0285 reg = <0x12000 0x1000>;
0286 };
0287
0288 =======================================================================
0289 Nexus Aurora Link Controller
0290
0291 This node represents the region of DCSR space allocated to
0292 the NAL Controller.
0293
0294 PROPERTIES
0295
0296 - compatible
0297 Usage: required
0298 Value type: <string>
0299 Definition: Must include both an identifier specific to the SoC
0300 or Debug IP of the form "fsl,<soc>-dcsr-nal" in addition to the
0301 generic compatible string "fsl,dcsr-nal".
0302
0303 - reg
0304 Usage: required
0305 Value type: <prop-encoded-array>
0306 Definition: A standard property. Specifies the physical address
0307 offset and length of the DCSR space registers of the device
0308 configuration block.
0309
0310 EXAMPLE
0311 dcsr-nal@18000 {
0312 compatible = "fsl,p4080-dcsr-nal", "fsl,dcsr-nal";
0313 reg = <0x18000 0x1000>;
0314 };
0315
0316
0317 =======================================================================
0318 Run Control and Power Management
0319
0320 This node represents the region of DCSR space allocated to
0321 the RCPM Debug Controller. This functionlity is limited to the
0322 control the debug operations of the SoC and cores.
0323
0324 PROPERTIES
0325
0326 - compatible
0327 Usage: required
0328 Value type: <string>
0329 Definition: Must include both an identifier specific to the SoC
0330 or Debug IP of the form "fsl,<soc>-dcsr-rcpm" in addition to the
0331 generic compatible string "fsl,dcsr-rcpm".
0332
0333 - reg
0334 Usage: required
0335 Value type: <prop-encoded-array>
0336 Definition: A standard property. Specifies the physical address
0337 offset and length of the DCSR space registers of the device
0338 configuration block.
0339
0340 EXAMPLE
0341 dcsr-rcpm@22000 {
0342 compatible = "fsl,p4080-dcsr-rcpm", "fsl,dcsr-rcpm";
0343 reg = <0x22000 0x1000>;
0344 };
0345
0346 =======================================================================
0347 Core Service Bridge Proxy
0348
0349 This node represents the region of DCSR space allocated to
0350 the Core Service Bridge Proxies.
0351 There is one Core Service Bridge Proxy device for each CPU in the system.
0352 This functionlity provides access to the debug operations of the CPU.
0353
0354 PROPERTIES
0355
0356 - compatible
0357 Usage: required
0358 Value type: <string>
0359 Definition: Must include both an identifier specific to the cpu
0360 of the form "fsl,dcsr-<cpu>-sb-proxy" in addition to the
0361 generic compatible string "fsl,dcsr-cpu-sb-proxy".
0362
0363 - cpu-handle
0364 Usage: required
0365 Definition: A phandle to associate this debug node with its cpu.
0366
0367 - reg
0368 Usage: required
0369 Value type: <prop-encoded-array>
0370 Definition: A standard property. Specifies the physical address
0371 offset and length of the DCSR space registers of the device
0372 configuration block.
0373
0374 EXAMPLE
0375 dcsr-cpu-sb-proxy@40000 {
0376 compatible = "fsl,dcsr-e500mc-sb-proxy",
0377 "fsl,dcsr-cpu-sb-proxy";
0378 cpu-handle = <&cpu0>;
0379 reg = <0x40000 0x1000>;
0380 };
0381 dcsr-cpu-sb-proxy@41000 {
0382 compatible = "fsl,dcsr-e500mc-sb-proxy",
0383 "fsl,dcsr-cpu-sb-proxy";
0384 cpu-handle = <&cpu1>;
0385 reg = <0x41000 0x1000>;
0386 };
0387
0388 =======================================================================
