0001 ===================================================================
0002 Power Architecture CPU Binding
0003 Copyright 2013 Freescale Semiconductor Inc.
0004
0005 Power Architecture CPUs in Freescale SOCs are represented in device trees as
0006 per the definition in the Devicetree Specification.
0007
0008 In addition to the Devicetree Specification definitions, the properties
0009 defined below may be present on CPU nodes.
0010
0011 PROPERTIES
0012
0013 - fsl,eref-*
0014 Usage: optional
0015 Value type: <empty>
0016 Definition: The EREF (EREF: A Programmer.s Reference Manual for
0017 Freescale Power Architecture) defines the architecture for Freescale
0018 Power CPUs. The EREF defines some architecture categories not defined
0019 by the Power ISA. For these EREF-specific categories, the existence of
0020 a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
0021 name with all uppercase letters converted to lowercase, indicates that
0022 the category is supported by the implementation.
0023
0024 - fsl,portid-mapping
0025 Usage: optional
0026 Value type: <u32>
0027 Definition: The Coherency Subdomain ID Port Mapping Registers and
0028 Snoop ID Port Mapping registers, which are part of the CoreNet
0029 Coherency fabric (CCF), provide a CoreNet Coherency Subdomain
0030 ID/CoreNet Snoop ID to cpu mapping functions. Certain bits from
0031 these registers should be set if the coresponding CPU should be
0032 snooped. This property defines a bitmask which selects the bit
0033 that should be set if this cpu should be snooped.
