0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/xlnx,zynqmp-psgtr.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Xilinx ZynqMP Gigabit Transceiver PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0011
0012 description: |
0013 This binding describes the Xilinx ZynqMP Gigabit Transceiver (GTR) PHY. The
0014 GTR provides four lanes and is used by USB, SATA, PCIE, Display port and
0015 Ethernet SGMII controllers.
0016
0017 properties:
0018 "#phy-cells":
0019 const: 4
0020 description: |
0021 The cells contain the following arguments.
0022
0023 - description: The GTR lane
0024 minimum: 0
0025 maximum: 3
0026 - description: The PHY type
0027 enum:
0028 - PHY_TYPE_DP
0029 - PHY_TYPE_PCIE
0030 - PHY_TYPE_SATA
0031 - PHY_TYPE_SGMII
0032 - PHY_TYPE_USB3
0033 - description: The PHY instance
0034 minimum: 0
0035 maximum: 1 # for DP, SATA or USB
0036 maximum: 3 # for PCIE or SGMII
0037 - description: The reference clock number
0038 minimum: 0
0039 maximum: 3
0040
0041 compatible:
0042 enum:
0043 - xlnx,zynqmp-psgtr-v1.1
0044 - xlnx,zynqmp-psgtr
0045
0046 clocks:
0047 minItems: 1
0048 maxItems: 4
0049 description: |
0050 Clock for each PS_MGTREFCLK[0-3] reference clock input. Unconnected
0051 inputs shall not have an entry.
0052
0053 clock-names:
0054 minItems: 1
0055 maxItems: 4
0056 items:
0057 pattern: "^ref[0-3]$"
0058
0059 reg:
0060 items:
0061 - description: SERDES registers block
0062 - description: SIOU registers block
0063
0064 reg-names:
0065 items:
0066 - const: serdes
0067 - const: siou
0068
0069 xlnx,tx-termination-fix:
0070 description: |
0071 Include this for fixing functional issue with the TX termination
0072 resistance in GT, which can be out of spec for the XCZU9EG silicon
0073 version.
0074 type: boolean
0075
0076 required:
0077 - "#phy-cells"
0078 - compatible
0079 - reg
0080 - reg-names
0081
0082 if:
0083 properties:
0084 compatible:
0085 const: xlnx,zynqmp-psgtr-v1.1
0086
0087 then:
0088 properties:
0089 xlnx,tx-termination-fix: false
0090
0091 additionalProperties: false
0092
0093 examples:
0094 - |
0095 phy: phy@fd400000 {
0096 compatible = "xlnx,zynqmp-psgtr-v1.1";
0097 reg = <0xfd400000 0x40000>,
0098 <0xfd3d0000 0x1000>;
0099 reg-names = "serdes", "siou";
0100 clocks = <&refclks 3>, <&refclks 2>, <&refclks 0>;
0101 clock-names = "ref1", "ref2", "ref3";
0102 #phy-cells = <4>;
0103 };
0104
0105 ...
