0001 TI PHY: DT DOCUMENTATION FOR PHYs in TI PLATFORMs
0002
0003 OMAP CONTROL PHY
0004
0005 Required properties:
0006 - compatible: Should be one of
0007 "ti,control-phy-otghs" - if it has otghs_control mailbox register as on OMAP4.
0008 "ti,control-phy-usb2" - if it has Power down bit in control_dev_conf register
0009 e.g. USB2_PHY on OMAP5.
0010 "ti,control-phy-pipe3" - if it has DPLL and individual Rx & Tx power control
0011 e.g. USB3 PHY and SATA PHY on OMAP5.
0012 "ti,control-phy-pcie" - for pcie to support external clock for pcie and to
0013 set PCS delay value.
0014 e.g. PCIE PHY in DRA7x
0015 "ti,control-phy-usb2-dra7" - if it has power down register like USB2 PHY on
0016 DRA7 platform.
0017 "ti,control-phy-usb2-am437" - if it has power down register like USB2 PHY on
0018 AM437 platform.
0019 - reg : register ranges as listed in the reg-names property
0020 - reg-names: "otghs_control" for control-phy-otghs
0021 "power", "pcie_pcs" and "control_sma" for control-phy-pcie
0022 "power" for all other types
0023
0024 omap_control_usb: omap-control-usb@4a002300 {
0025 compatible = "ti,control-phy-otghs";
0026 reg = <0x4a00233c 0x4>;
0027 reg-names = "otghs_control";
0028 };
0029
0030 TI PIPE3 PHY
0031
0032 Required properties:
0033 - compatible: Should be "ti,phy-usb3", "ti,phy-pipe3-sata" or
0034 "ti,phy-pipe3-pcie. "ti,omap-usb3" is deprecated.
0035 - reg : Address and length of the register set for the device.
0036 - reg-names: The names of the register addresses corresponding to the registers
0037 filled in "reg".
0038 - #phy-cells: determine the number of cells that should be given in the
0039 phandle while referencing this phy.
0040 - clocks: a list of phandles and clock-specifier pairs, one for each entry in
0041 clock-names.
0042 - clock-names: should include:
0043 * "wkupclk" - wakeup clock.
0044 * "sysclk" - system clock.
0045 * "refclk" - reference clock.
0046 * "dpll_ref" - external dpll ref clk
0047 * "dpll_ref_m2" - external dpll ref clk
0048 * "phy-div" - divider for apll
0049 * "div-clk" - apll clock
0050
0051 Optional properties:
0052 - id: If there are multiple instance of the same type, in order to
0053 differentiate between each instance "id" can be used (e.g., multi-lane PCIe
0054 PHY). If "id" is not provided, it is set to default value of '1'.
0055 - syscon-pllreset: Handle to system control region that contains the
0056 CTRL_CORE_SMA_SW_0 register and register offset to the CTRL_CORE_SMA_SW_0
0057 register that contains the SATA_PLL_SOFT_RESET bit. Only valid for sata_phy.
0058 - syscon-pcs : phandle/offset pair. Phandle to the system control module and the
0059 register offset to write the PCS delay value.
0060
0061 Deprecated properties:
0062 - ctrl-module : phandle of the control module used by PHY driver to power on
0063 the PHY.
0064
0065 Recommended properies:
0066 - syscon-phy-power : phandle/offset pair. Phandle to the system control
0067 module and the register offset to power on/off the PHY.
0068
0069 This is usually a subnode of ocp2scp to which it is connected.
0070
0071 usb3phy@4a084400 {
0072 compatible = "ti,phy-usb3";
0073 reg = <0x4a084400 0x80>,
0074 <0x4a084800 0x64>,
0075 <0x4a084c00 0x40>;
0076 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
0077 ctrl-module = <&omap_control_usb>;
0078 #phy-cells = <0>;
0079 clocks = <&usb_phy_cm_clk32k>,
0080 <&sys_clkin>,
0081 <&usb_otg_ss_refclk960m>;
0082 clock-names = "wkupclk",
0083 "sysclk",
0084 "refclk";
0085 };
0086
0087 sata_phy: phy@4a096000 {
0088 compatible = "ti,phy-pipe3-sata";
0089 reg = <0x4A096000 0x80>, /* phy_rx */
0090 <0x4A096400 0x64>, /* phy_tx */
0091 <0x4A096800 0x40>; /* pll_ctrl */
0092 reg-names = "phy_rx", "phy_tx", "pll_ctrl";
0093 ctrl-module = <&omap_control_sata>;
0094 clocks = <&sys_clkin1>, <&sata_ref_clk>;
0095 clock-names = "sysclk", "refclk";
0096 syscon-pllreset = <&scm_conf 0x3fc>;
0097 #phy-cells = <0>;
0098 };
