0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/phy/ti,phy-j721e-wiz.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: TI J721E WIZ (SERDES Wrapper)
0009
0010 maintainers:
0011 - Kishon Vijay Abraham I <kishon@ti.com>
0012
0013 properties:
0014 compatible:
0015 enum:
0016 - ti,j721e-wiz-16g
0017 - ti,j721e-wiz-10g
0018 - ti,am64-wiz-10g
0019
0020 power-domains:
0021 maxItems: 1
0022
0023 clocks:
0024 maxItems: 3
0025 description: clock-specifier to represent input to the WIZ
0026
0027 clock-names:
0028 items:
0029 - const: fck
0030 - const: core_ref_clk
0031 - const: ext_ref_clk
0032
0033 num-lanes:
0034 minimum: 1
0035 maximum: 4
0036
0037 "#address-cells":
0038 const: 1
0039
0040 "#size-cells":
0041 const: 1
0042
0043 "#reset-cells":
0044 const: 1
0045
0046 "#clock-cells":
0047 const: 1
0048
0049 ranges: true
0050
0051 assigned-clocks:
0052 minItems: 1
0053 maxItems: 2
0054
0055 assigned-clock-parents:
0056 minItems: 1
0057 maxItems: 2
0058
0059 assigned-clock-rates:
0060 minItems: 1
0061 maxItems: 2
0062
0063 typec-dir-gpios:
0064 maxItems: 1
0065 description:
0066 GPIO to signal Type-C cable orientation for lane swap.
0067 If GPIO is active, lane 0 and lane 1 of SERDES will be swapped to
0068 achieve the funtionality of an external type-C plug flip mux.
0069
0070 typec-dir-debounce-ms:
0071 minimum: 100
0072 maximum: 1000
0073 default: 100
0074 description:
0075 Number of milliseconds to wait before sampling typec-dir-gpio.
0076 If not specified, the default debounce of 100ms will be used.
0077 Type-C spec states minimum CC pin debounce of 100 ms and maximum
0078 of 200 ms. However, some solutions might need more than 200 ms.
0079
0080 refclk-dig:
0081 type: object
0082 description: |
0083 WIZ node should have subnode for refclk_dig to select the reference
0084 clock source for the reference clock used in the PHY and PMA digital
0085 logic.
0086 properties:
0087 clocks:
0088 minItems: 2
0089 maxItems: 4
0090 description: Phandle to two (Torrent) or four (Sierra) clock nodes representing
0091 the inputs to refclk_dig
0092
0093 "#clock-cells":
0094 const: 0
0095
0096 assigned-clocks:
0097 maxItems: 1
0098
0099 assigned-clock-parents:
0100 maxItems: 1
0101
0102 required:
0103 - clocks
0104 - "#clock-cells"
0105 - assigned-clocks
0106 - assigned-clock-parents
0107
0108 patternProperties:
0109 "^pll[0|1]-refclk$":
0110 type: object
0111 description: |
0112 WIZ node should have subnodes for each of the PLLs present in
0113 the SERDES.
0114 properties:
0115 clocks:
0116 maxItems: 2
0117 description: Phandle to clock nodes representing the two inputs to PLL.
0118
0119 "#clock-cells":
0120 const: 0
0121
0122 assigned-clocks:
0123 maxItems: 1
0124
0125 assigned-clock-parents:
0126 maxItems: 1
0127
0128 required:
0129 - clocks
0130 - "#clock-cells"
0131 - assigned-clocks
0132 - assigned-clock-parents
0133
0134 "^cmn-refclk1?-dig-div$":
0135 type: object
0136 description:
0137 WIZ node should have subnodes for each of the PMA common refclock
0138 provided by the SERDES.
0139 properties:
0140 clocks:
0141 maxItems: 1
0142 description: Phandle to the clock node representing the input to the
0143 divider clock.
0144
0145 "#clock-cells":
0146 const: 0
0147
0148 required:
0149 - clocks
0150 - "#clock-cells"
0151
0152 "^serdes@[0-9a-f]+$":
0153 type: object
0154 description: |
0155 WIZ node should have '1' subnode for the SERDES. It could be either
0156 Sierra SERDES or Torrent SERDES. Sierra SERDES should follow the
0157 bindings specified in
0158 Documentation/devicetree/bindings/phy/phy-cadence-sierra.yaml
0159 Torrent SERDES should follow the bindings specified in
0160 Documentation/devicetree/bindings/phy/phy-cadence-torrent.yaml
0161
0162 required:
0163 - compatible
0164 - power-domains
0165 - clocks
0166 - clock-names
0167 - num-lanes
0168 - "#address-cells"
0169 - "#size-cells"
0170 - "#reset-cells"
0171 - ranges
0172
0173 additionalProperties: false
0174
0175 examples:
0176 - |
0177 #include <dt-bindings/soc/ti,sci_pm_domain.h>
0178
0179 wiz@5000000 {
0180 compatible = "ti,j721e-wiz-16g";
0181 #address-cells = <1>;
0182 #size-cells = <1>;
0183 power-domains = <&k3_pds 292 TI_SCI_PD_EXCLUSIVE>;
0184 clocks = <&k3_clks 292 5>, <&k3_clks 292 11>, <&dummy_cmn_refclk>;
0185 clock-names = "fck", "core_ref_clk", "ext_ref_clk";
0186 assigned-clocks = <&k3_clks 292 11>, <&k3_clks 292 0>;
0187 assigned-clock-parents = <&k3_clks 292 15>, <&k3_clks 292 4>;
0188 num-lanes = <2>;
0189 #reset-cells = <1>;
0190 ranges = <0x5000000 0x5000000 0x10000>;
0191
0192 pll0-refclk {
0193 clocks = <&k3_clks 293 13>, <&dummy_cmn_refclk>;
0194 #clock-cells = <0>;
0195 assigned-clocks = <&wiz1_pll0_refclk>;
0196 assigned-clock-parents = <&k3_clks 293 13>;
0197 };
0198
0199 pll1-refclk {
0200 clocks = <&k3_clks 293 0>, <&dummy_cmn_refclk1>;
0201 #clock-cells = <0>;
0202 assigned-clocks = <&wiz1_pll1_refclk>;
0203 assigned-clock-parents = <&k3_clks 293 0>;
0204 };
0205
0206 cmn-refclk-dig-div {
0207 clocks = <&wiz1_refclk_dig>;
0208 #clock-cells = <0>;
0209 };
0210
0211 cmn-refclk1-dig-div {
0212 clocks = <&wiz1_pll1_refclk>;
0213 #clock-cells = <0>;
0214 };
0215
0216 refclk-dig {
0217 clocks = <&k3_clks 292 11>, <&k3_clks 292 0>,
0218 <&dummy_cmn_refclk>, <&dummy_cmn_refclk1>;
0219 #clock-cells = <0>;
0220 assigned-clocks = <&wiz0_refclk_dig>;
0221 assigned-clock-parents = <&k3_clks 292 11>;
0222 };
0223
0224 serdes@5000000 {
0225 compatible = "ti,sierra-phy-t0";
0226 reg-names = "serdes";
0227 reg = <0x5000000 0x10000>;
0228 #address-cells = <1>;
0229 #size-cells = <0>;
0230 resets = <&serdes_wiz0 0>;
0231 reset-names = "sierra_reset";
0232 clocks = <&wiz0_cmn_refclk_dig_div>, <&wiz0_cmn_refclk1_dig_div>;
0233 clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
0234 };
0235 };
