bindings/phy/ti%2Cphy-gmii-sel.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/phy/ti,phy-gmii-sel.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: CPSW Port's Interface Mode Selection PHY Tree Bindings
0009
0010 maintainers:
0011   - Kishon Vijay Abraham I <kishon@ti.com>
0012
0013 description: |
0014   TI am335x/am437x/dra7(am5)/dm814x CPSW3G Ethernet Subsystem supports
0015   two 10/100/1000 Ethernet ports with selectable G/MII, RMII, and RGMII interfaces.
0016   The interface mode is selected by configuring the MII mode selection register(s)
0017   (GMII_SEL) in the System Control Module chapter (SCM). GMII_SEL register(s) and
0018   bit fields placement in SCM are different between SoCs while fields meaning
0019   is the same.
0020                                                +--------------+
0021         +-------------------------------+      |SCM           |
0022         |                     CPSW      |      |  +---------+ |
0023         |        +--------------------------------+gmii_sel | |
0024         |        |                      |      |  +---------+ |
0025         |   +----v---+     +--------+   |      +--------------+
0026         |   |Port 1..<--+-->GMII/MII<------->
0027         |   |        |  |  |        |   |
0028         |   +--------+  |  +--------+   |
0029         |               |               |
0030         |               |  +--------+   |
0031         |               |  | RMII   <------->
0032         |               +-->        |   |
0033         |               |  +--------+   |
0034         |               |               |
0035         |               |  +--------+   |
0036         |               |  | RGMII  <------->
0037         |               +-->        |   |
0038         |                  +--------+   |
0039         +-------------------------------+
0040
0041   CPSW Port's Interface Mode Selection PHY describes MII interface mode between
0042   CPSW Port and Ethernet PHY which depends on Eth PHY and board configuration.
0043   |
0044   CPSW Port's Interface Mode Selection PHY device should defined as child device
0045   of SCM node (scm_conf) and can be attached to each CPSW port node using standard
0046   PHY bindings.
0047
0048 properties:
0049   compatible:
0050     enum:
0051       - ti,am3352-phy-gmii-sel
0052       - ti,dra7xx-phy-gmii-sel
0053       - ti,am43xx-phy-gmii-sel
0054       - ti,dm814-phy-gmii-sel
0055       - ti,am654-phy-gmii-sel
0056
0057   reg:
0058     maxItems: 1
0059
0060   '#phy-cells': true
0061
0062 allOf:
0063   - if:
0064       properties:
0065         compatible:
0066           contains:
0067             enum:
0068               - ti,dra7xx-phy-gmii-sel
0069               - ti,dm814-phy-gmii-sel
0070               - ti,am654-phy-gmii-sel
0071     then:
0072       properties:
0073         '#phy-cells':
0074           const: 1
0075           description: CPSW port number (starting from 1)
0076   - if:
0077       properties:
0078         compatible:
0079           contains:
0080             enum:
0081               - ti,am3352-phy-gmii-sel
0082               - ti,am43xx-phy-gmii-sel
0083     then:
0084       properties:
0085         '#phy-cells':
0086           const: 2
0087           description: |
0088             - CPSW port number (starting from 1)
0089             - RMII refclk mode
0090
0091 required:
0092   - compatible
0093   - reg
0094   - '#phy-cells'
0095
0096 additionalProperties: false
0097
0098 examples:
0099   - |
0100     phy_gmii_sel: phy-gmii-sel@650 {
0101         compatible = "ti,am3352-phy-gmii-sel";
0102         reg = <0x650 0x4>;
0103         #phy-cells = <2>;
0104     };