0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/socionext,uniphier-usb3hs-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Socionext UniPhier USB3 High-Speed (HS) PHY
0008
0009 description: |
0010 This describes the devicetree bindings for PHY interfaces built into
0011 USB3 controller implemented on Socionext UniPhier SoCs.
0012 Although the controller includes High-Speed PHY and Super-Speed PHY,
0013 this describes about High-Speed PHY.
0014
0015 maintainers:
0016 - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
0017
0018 properties:
0019 compatible:
0020 enum:
0021 - socionext,uniphier-pro5-usb3-hsphy
0022 - socionext,uniphier-pxs2-usb3-hsphy
0023 - socionext,uniphier-ld20-usb3-hsphy
0024 - socionext,uniphier-pxs3-usb3-hsphy
0025 - socionext,uniphier-nx1-usb3-hsphy
0026
0027 reg:
0028 maxItems: 1
0029
0030 "#phy-cells":
0031 const: 0
0032
0033 clocks:
0034 minItems: 2
0035 maxItems: 3
0036
0037 clock-names: true
0038
0039 resets:
0040 maxItems: 2
0041
0042 reset-names: true
0043
0044 vbus-supply:
0045 description: A phandle to the regulator for USB VBUS
0046
0047 nvmem-cells:
0048 maxItems: 3
0049 description:
0050 Phandles to nvmem cell that contains the trimming data.
0051 Available only for HS-PHY implemented on LD20 and PXs3, and
0052 if unspecified, default value is used.
0053
0054 nvmem-cell-names:
0055 items:
0056 - const: rterm
0057 - const: sel_t
0058 - const: hs_i
0059 description:
0060 Should be the following names, which correspond to each nvmem-cells.
0061 All of the 3 parameters associated with the above names are
0062 required for each port, if any one is omitted, the trimming data
0063 of the port will not be set at all.
0064
0065 allOf:
0066 - if:
0067 properties:
0068 compatible:
0069 contains:
0070 const: socionext,uniphier-pro5-usb3-hsphy
0071 then:
0072 properties:
0073 clocks:
0074 minItems: 2
0075 maxItems: 2
0076 clock-names:
0077 items:
0078 - const: gio
0079 - const: link
0080 resets:
0081 minItems: 2
0082 maxItems: 2
0083 reset-names:
0084 items:
0085 - const: gio
0086 - const: link
0087 - if:
0088 properties:
0089 compatible:
0090 contains:
0091 enum:
0092 - socionext,uniphier-pxs2-usb3-hsphy
0093 - socionext,uniphier-ld20-usb3-hsphy
0094 then:
0095 properties:
0096 clocks:
0097 minItems: 2
0098 maxItems: 2
0099 clock-names:
0100 items:
0101 - const: link
0102 - const: phy
0103 resets:
0104 minItems: 2
0105 maxItems: 2
0106 reset-names:
0107 items:
0108 - const: link
0109 - const: phy
0110 - if:
0111 properties:
0112 compatible:
0113 contains:
0114 enum:
0115 - socionext,uniphier-pxs3-usb3-hsphy
0116 - socionext,uniphier-nx1-usb3-hsphy
0117 then:
0118 properties:
0119 clocks:
0120 minItems: 2
0121 maxItems: 3
0122 clock-names:
0123 minItems: 2
0124 items:
0125 - const: link
0126 - const: phy
0127 - const: phy-ext
0128 resets:
0129 minItems: 2
0130 maxItems: 2
0131 reset-names:
0132 items:
0133 - const: link
0134 - const: phy
0135
0136 required:
0137 - compatible
0138 - reg
0139 - "#phy-cells"
0140 - clocks
0141 - clock-names
0142 - resets
0143 - reset-names
0144
0145 additionalProperties: false
0146
0147 examples:
0148 - |
0149 usb-glue@65b00000 {
0150 compatible = "socionext,uniphier-ld20-dwc3-glue", "simple-mfd";
0151 #address-cells = <1>;
0152 #size-cells = <1>;
0153 ranges = <0 0x65b00000 0x400>;
0154
0155 usb_hsphy0: hs-phy@200 {
0156 compatible = "socionext,uniphier-ld20-usb3-hsphy";
0157 reg = <0x200 0x10>;
0158 #phy-cells = <0>;
0159 clock-names = "link", "phy";
0160 clocks = <&sys_clk 14>, <&sys_clk 16>;
0161 reset-names = "link", "phy";
0162 resets = <&sys_rst 14>, <&sys_rst 16>;
0163 vbus-supply = <&usb_vbus0>;
0164 nvmem-cell-names = "rterm", "sel_t", "hs_i";
0165 nvmem-cells = <&usb_rterm0>, <&usb_sel_t0>, <&usb_hs_i0>;
0166 };
0167 };
