bindings/phy/socionext%2Cuniphier-pcie-phy.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/socionext,uniphier-pcie-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Socionext UniPhier PCIe PHY
0008
0009 description: |
0010   This describes the devicetree bindings for PHY interface built into
0011   PCIe controller implemented on Socionext UniPhier SoCs.
0012
0013 maintainers:
0014   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
0015
0016 properties:
0017   compatible:
0018     enum:
0019       - socionext,uniphier-pro5-pcie-phy
0020       - socionext,uniphier-ld20-pcie-phy
0021       - socionext,uniphier-pxs3-pcie-phy
0022       - socionext,uniphier-nx1-pcie-phy
0023
0024   reg:
0025     maxItems: 1
0026
0027   "#phy-cells":
0028     const: 0
0029
0030   clocks:
0031     minItems: 1
0032     maxItems: 2
0033
0034   clock-names: true
0035
0036   resets:
0037     minItems: 1
0038     maxItems: 2
0039
0040   reset-names: true
0041
0042   socionext,syscon:
0043     $ref: /schemas/types.yaml#/definitions/phandle
0044     description: A phandle to system control to set configurations for phy
0045
0046 allOf:
0047   - if:
0048       properties:
0049         compatible:
0050           contains:
0051             const: socionext,uniphier-pro5-pcie-phy
0052     then:
0053       properties:
0054         clocks:
0055           minItems: 2
0056           maxItems: 2
0057         clock-names:
0058           items:
0059             - const: gio
0060             - const: link
0061         resets:
0062           minItems: 2
0063           maxItems: 2
0064         reset-names:
0065           items:
0066             - const: gio
0067             - const: link
0068     else:
0069       properties:
0070         clocks:
0071           maxItems: 1
0072         clock-names:
0073           const: link
0074         resets:
0075           maxItems: 1
0076         reset-names:
0077           const: link
0078
0079 required:
0080   - compatible
0081   - reg
0082   - "#phy-cells"
0083   - clocks
0084   - clock-names
0085   - resets
0086   - reset-names
0087
0088 additionalProperties: false
0089
0090 examples:
0091   - |
0092     pcie_phy: phy@66038000 {
0093         compatible = "socionext,uniphier-ld20-pcie-phy";
0094         reg = <0x66038000 0x4000>;
0095         #phy-cells = <0>;
0096         clock-names = "link";
0097         clocks = <&sys_clk 24>;
0098         reset-names = "link";
0099         resets = <&sys_rst 24>;
0100         socionext,syscon = <&soc_glue>;
0101     };