bindings/phy/samsung%2Cusb3-drd-phy.yaml

0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/samsung,usb3-drd-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung Exynos SoC USB 3.0 DRD PHY USB 2.0 PHY
0008
0009 maintainers:
0010   - Krzysztof Kozlowski <krzk@kernel.org>
0011   - Marek Szyprowski <m.szyprowski@samsung.com>
0012   - Sylwester Nawrocki <s.nawrocki@samsung.com>
0013
0014 description: |
0015   For samsung,exynos5250-usbdrd-phy and samsung,exynos5420-usbdrd-phy
0016   compatible PHYs, the second cell in the PHY specifier identifies the
0017   PHY id, which is interpreted as follows::
0018     0 - UTMI+ type phy,
0019     1 - PIPE3 type phy.
0020
0021   For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
0022   'usbdrd_phy' nodes should have numbered alias in the aliases node, in the
0023   form of usbdrdphyN, N = 0, 1... (depending on number of controllers).
0024
0025 properties:
0026   compatible:
0027     enum:
0028       - samsung,exynos5250-usbdrd-phy
0029       - samsung,exynos5420-usbdrd-phy
0030       - samsung,exynos5433-usbdrd-phy
0031       - samsung,exynos7-usbdrd-phy
0032
0033   clocks:
0034     minItems: 2
0035     maxItems: 5
0036
0037   clock-names:
0038     minItems: 2
0039     maxItems: 5
0040     description: |
0041       At least two clocks::
0042         - Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
0043           for register access.
0044         - PHY reference clock (usually crystal clock), used for PHY operations,
0045           associated by phy name. It is used to determine bit values for clock
0046           settings register.  For Exynos5420 this is given as 'sclk_usbphy30'
0047           in the CMU.
0048
0049   "#phy-cells":
0050     const: 1
0051
0052   port:
0053     $ref: /schemas/graph.yaml#/properties/port
0054     description:
0055       Any connector to the data bus of this controller should be modelled using
0056       the OF graph bindings specified.
0057
0058   reg:
0059     maxItems: 1
0060
0061   samsung,pmu-syscon:
0062     $ref: /schemas/types.yaml#/definitions/phandle
0063     description:
0064       Phandle to PMU system controller interface.
0065
0066   vbus-supply:
0067     description:
0068       VBUS power source.
0069
0070   vbus-boost-supply:
0071     description:
0072       VBUS Boost 5V power source.
0073
0074 required:
0075   - compatible
0076   - clocks
0077   - clock-names
0078   - "#phy-cells"
0079   - reg
0080   - samsung,pmu-syscon
0081
0082 allOf:
0083   - if:
0084       properties:
0085         compatible:
0086           contains:
0087             enum:
0088               - samsung,exynos5433-usbdrd-phy
0089               - samsung,exynos7-usbdrd-phy
0090     then:
0091       properties:
0092         clocks:
0093           minItems: 5
0094           maxItems: 5
0095         clock-names:
0096           items:
0097             - const: phy
0098             - const: ref
0099             - const: phy_utmi
0100             - const: phy_pipe
0101             - const: itp
0102     else:
0103       properties:
0104         clocks:
0105           minItems: 2
0106           maxItems: 2
0107         clock-names:
0108           items:
0109             - const: phy
0110             - const: ref
0111
0112 additionalProperties: false
0113
0114 examples:
0115   - |
0116     #include <dt-bindings/clock/exynos5420.h>
0117
0118     phy@12100000 {
0119         compatible = "samsung,exynos5420-usbdrd-phy";
0120         reg = <0x12100000 0x100>;
0121         #phy-cells = <1>;
0122         clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBPHY300>;
0123         clock-names = "phy", "ref";
0124         samsung,pmu-syscon = <&pmu_system_controller>;
0125         vbus-supply = <&usb300_vbus_reg>;
0126     };