0001 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/samsung,ufs-phy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Samsung SoC series UFS PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Alim Akhtar <alim.akhtar@samsung.com>
0011
0012 properties:
0013 "#phy-cells":
0014 const: 0
0015
0016 compatible:
0017 enum:
0018 - samsung,exynos7-ufs-phy
0019 - samsung,exynosautov9-ufs-phy
0020 - tesla,fsd-ufs-phy
0021
0022 reg:
0023 maxItems: 1
0024
0025 reg-names:
0026 items:
0027 - const: phy-pma
0028
0029 clocks:
0030 items:
0031 - description: PLL reference clock
0032 - description: symbol clock for input symbol ( rx0-ch0 symbol clock)
0033 - description: symbol clock for input symbol ( rx1-ch1 symbol clock)
0034 - description: symbol clock for output symbol ( tx0 symbol clock)
0035
0036 clock-names:
0037 items:
0038 - const: ref_clk
0039 - const: rx1_symbol_clk
0040 - const: rx0_symbol_clk
0041 - const: tx0_symbol_clk
0042
0043 samsung,pmu-syscon:
0044 $ref: '/schemas/types.yaml#/definitions/phandle-array'
0045 maxItems: 1
0046 items:
0047 minItems: 1
0048 items:
0049 - description: phandle for PMU system controller interface, used to
0050 control pmu registers bits for ufs m-phy
0051 - description: offset of the pmu control register
0052 description:
0053 It can be phandle/offset pair. The second cell which can represent an
0054 offset is optional.
0055
0056 required:
0057 - "#phy-cells"
0058 - compatible
0059 - reg
0060 - reg-names
0061 - clocks
0062 - clock-names
0063 - samsung,pmu-syscon
0064
0065 additionalProperties: false
0066
0067 examples:
0068 - |
0069 #include <dt-bindings/clock/exynos7-clk.h>
0070
0071 ufs_phy: ufs-phy@15571800 {
0072 compatible = "samsung,exynos7-ufs-phy";
0073 reg = <0x15571800 0x240>;
0074 reg-names = "phy-pma";
0075 samsung,pmu-syscon = <&pmu_system_controller>;
0076 #phy-cells = <0>;
0077 clocks = <&clock_fsys1 SCLK_COMBO_PHY_EMBEDDED_26M>,
0078 <&clock_fsys1 PHYCLK_UFS20_RX1_SYMBOL_USER>,
0079 <&clock_fsys1 PHYCLK_UFS20_RX0_SYMBOL_USER>,
0080 <&clock_fsys1 PHYCLK_UFS20_TX0_SYMBOL_USER>;
0081 clock-names = "ref_clk", "rx1_symbol_clk",
0082 "rx0_symbol_clk", "tx0_symbol_clk";
0083
0084 };
0085 ...
