0001 # SPDX-License-Identifier: (GPL-2.0+ OR MIT)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/rockchip-mipi-dphy-rx0.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Helen Koike <helen.koike@collabora.com>
0011 - Ezequiel Garcia <ezequiel@collabora.com>
0012
0013 description: |
0014 The Rockchip SoC has a MIPI D-PHY bus with an RX0 entry which connects to
0015 the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
0016
0017 properties:
0018 compatible:
0019 const: rockchip,rk3399-mipi-dphy-rx0
0020
0021 clocks:
0022 items:
0023 - description: MIPI D-PHY ref clock
0024 - description: MIPI D-PHY RX0 cfg clock
0025 - description: Video in/out general register file clock
0026
0027 clock-names:
0028 items:
0029 - const: dphy-ref
0030 - const: dphy-cfg
0031 - const: grf
0032
0033 '#phy-cells':
0034 const: 0
0035
0036 power-domains:
0037 description: Video in/out power domain.
0038 maxItems: 1
0039
0040 required:
0041 - compatible
0042 - clocks
0043 - clock-names
0044 - '#phy-cells'
0045 - power-domains
0046
0047 additionalProperties: false
0048
0049 examples:
0050 - |
0051
0052 /*
0053 * MIPI D-PHY RX0 use registers in "general register files", it
0054 * should be a child of the GRF.
0055 *
0056 * grf: syscon@ff770000 {
0057 * compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
0058 * ...
0059 * };
0060 */
0061
0062 #include <dt-bindings/clock/rk3399-cru.h>
0063 #include <dt-bindings/power/rk3399-power.h>
0064
0065 mipi_dphy_rx0: mipi-dphy-rx0 {
0066 compatible = "rockchip,rk3399-mipi-dphy-rx0";
0067 clocks = <&cru SCLK_MIPIDPHY_REF>,
0068 <&cru SCLK_DPHY_RX0_CFG>,
0069 <&cru PCLK_VIO_GRF>;
0070 clock-names = "dphy-ref", "dphy-cfg", "grf";
0071 power-domains = <&power RK3399_PD_VIO>;
0072 #phy-cells = <0>;
0073 };
