0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/rockchip-inno-csi-dphy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip SoC MIPI RX0 D-PHY Device Tree Bindings
0008
0009 maintainers:
0010 - Heiko Stuebner <heiko@sntech.de>
0011
0012 description: |
0013 The Rockchip SoC has a MIPI CSI D-PHY based on an Innosilicon IP wich
0014 connects to the ISP1 (Image Signal Processing unit v1.0) for CSI cameras.
0015
0016 properties:
0017 compatible:
0018 enum:
0019 - rockchip,px30-csi-dphy
0020 - rockchip,rk1808-csi-dphy
0021 - rockchip,rk3326-csi-dphy
0022 - rockchip,rk3368-csi-dphy
0023
0024 reg:
0025 maxItems: 1
0026
0027 clocks:
0028 maxItems: 1
0029
0030 clock-names:
0031 const: pclk
0032
0033 '#phy-cells':
0034 const: 0
0035
0036 power-domains:
0037 description: Video in/out power domain.
0038 maxItems: 1
0039
0040 resets:
0041 items:
0042 - description: exclusive PHY reset line
0043
0044 reset-names:
0045 items:
0046 - const: apb
0047
0048 rockchip,grf:
0049 $ref: /schemas/types.yaml#/definitions/phandle
0050 description:
0051 Some additional phy settings are access through GRF regs.
0052
0053 required:
0054 - compatible
0055 - reg
0056 - clocks
0057 - clock-names
0058 - '#phy-cells'
0059 - power-domains
0060 - resets
0061 - reset-names
0062 - rockchip,grf
0063
0064 additionalProperties: false
0065
0066 examples:
0067 - |
0068
0069 csi_dphy: phy@ff2f0000 {
0070 compatible = "rockchip,px30-csi-dphy";
0071 reg = <0xff2f0000 0x4000>;
0072 clocks = <&cru 1>;
0073 clock-names = "pclk";
0074 #phy-cells = <0>;
0075 power-domains = <&power 1>;
0076 resets = <&cru 1>;
0077 reset-names = "apb";
0078 rockchip,grf = <&grf>;
0079 };
