0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/rockchip,px30-dsi-dphy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip MIPI DPHY with additional LVDS/TTL modes
0008
0009 maintainers:
0010 - Heiko Stuebner <heiko@sntech.de>
0011
0012 properties:
0013 "#phy-cells":
0014 const: 0
0015
0016 compatible:
0017 enum:
0018 - rockchip,px30-dsi-dphy
0019 - rockchip,rk3128-dsi-dphy
0020 - rockchip,rk3368-dsi-dphy
0021
0022 reg:
0023 maxItems: 1
0024
0025 clocks:
0026 items:
0027 - description: PLL reference clock
0028 - description: Module clock
0029
0030 clock-names:
0031 items:
0032 - const: ref
0033 - const: pclk
0034
0035 power-domains:
0036 maxItems: 1
0037 description: phandle to the associated power domain
0038
0039 resets:
0040 items:
0041 - description: exclusive PHY reset line
0042
0043 reset-names:
0044 items:
0045 - const: apb
0046
0047 required:
0048 - "#phy-cells"
0049 - compatible
0050 - reg
0051 - clocks
0052 - clock-names
0053 - resets
0054 - reset-names
0055
0056 additionalProperties: false
0057
0058 examples:
0059 - |
0060 dsi_dphy: phy@ff2e0000 {
0061 compatible = "rockchip,px30-dsi-dphy";
0062 reg = <0xff2e0000 0x10000>;
0063 clocks = <&pmucru 13>, <&cru 12>;
0064 clock-names = "ref", "pclk";
0065 resets = <&cru 12>;
0066 reset-names = "apb";
0067 #phy-cells = <0>;
0068 };
0069
0070 ...
