0001 Qualcomm PCIe2 PHY controller
0002 =============================
0003
0004 The Qualcomm PCIe2 PHY is a Synopsys based phy found in a number of Qualcomm
0005 platforms.
0006
0007 Required properties:
0008 - compatible: compatible list, should be:
0009 "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy"
0010
0011 - reg: offset and length of the PHY register set.
0012 - #phy-cells: must be 0.
0013
0014 - clocks: a clock-specifier pair for the "pipe" clock
0015
0016 - vdda-vp-supply: phandle to low voltage regulator
0017 - vdda-vph-supply: phandle to high voltage regulator
0018
0019 - resets: reset-specifier pairs for the "phy" and "pipe" resets
0020 - reset-names: list of resets, should contain:
0021 "phy" and "pipe"
0022
0023 - clock-output-names: name of the outgoing clock signal from the PHY PLL
0024 - #clock-cells: must be 0
0025
0026 Example:
0027 phy@7786000 {
0028 compatible = "qcom,qcs404-pcie2-phy", "qcom,pcie2-phy";
0029 reg = <0x07786000 0xb8>;
0030
0031 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
0032 resets = <&gcc GCC_PCIEPHY_0_PHY_BCR>,
0033 <&gcc GCC_PCIE_0_PIPE_ARES>;
0034 reset-names = "phy", "pipe";
0035
0036 vdda-vp-supply = <&vreg_l3_1p05>;
0037 vdda-vph-supply = <&vreg_l5_1p8>;
0038
0039 clock-output-names = "pcie_0_pipe_clk";
0040 #clock-cells = <0>;
0041 #phy-cells = <0>;
0042 };
