bindings/phy/qcom%2Cqusb2-phy.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/phy/qcom,qusb2-phy.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Qualcomm QUSB2 phy controller
0009
0010 maintainers:
0011   - Wesley Cheng <quic_wcheng@quicinc.com>
0012
0013 description:
0014   QUSB2 controller supports LS/FS/HS usb connectivity on Qualcomm chipsets.
0015
0016 properties:
0017   compatible:
0018     oneOf:
0019       - items:
0020           - enum:
0021               - qcom,ipq8074-qusb2-phy
0022               - qcom,msm8953-qusb2-phy
0023               - qcom,msm8996-qusb2-phy
0024               - qcom,msm8998-qusb2-phy
0025               - qcom,qcm2290-qusb2-phy
0026               - qcom,sdm660-qusb2-phy
0027               - qcom,ipq6018-qusb2-phy
0028               - qcom,sm4250-qusb2-phy
0029               - qcom,sm6115-qusb2-phy
0030       - items:
0031           - enum:
0032               - qcom,sc7180-qusb2-phy
0033               - qcom,sdm845-qusb2-phy
0034               - qcom,sm6350-qusb2-phy
0035           - const: qcom,qusb2-v2-phy
0036   reg:
0037     maxItems: 1
0038
0039   "#phy-cells":
0040     const: 0
0041
0042   clocks:
0043     minItems: 2
0044     items:
0045       - description: phy config clock
0046       - description: 19.2 MHz ref clk
0047       - description: phy interface clock (Optional)
0048
0049   clock-names:
0050     minItems: 2
0051     items:
0052       - const: cfg_ahb
0053       - const: ref
0054       - const: iface
0055
0056   vdd-supply:
0057     description:
0058       Phandle to 0.9V regulator supply to PHY digital circuit.
0059
0060   vdda-pll-supply:
0061     description:
0062       Phandle to 1.8V regulator supply to PHY refclk pll block.
0063
0064   vdda-phy-dpdm-supply:
0065     description:
0066       Phandle to 3.1V regulator supply to Dp/Dm port signals.
0067
0068   resets:
0069     maxItems: 1
0070     description:
0071       Phandle to reset to phy block.
0072
0073   nvmem-cells:
0074     maxItems: 1
0075     description:
0076       Phandle to nvmem cell that contains 'HS Tx trim'
0077       tuning parameter value for qusb2 phy.
0078
0079   qcom,tcsr-syscon:
0080     description:
0081       Phandle to TCSR syscon register region.
0082     $ref: /schemas/types.yaml#/definitions/phandle
0083
0084 if:
0085   properties:
0086     compatible:
0087       contains:
0088         const: qcom,qusb2-v2-phy
0089 then:
0090   properties:
0091     qcom,imp-res-offset-value:
0092       description:
0093         It is a 6 bit value that specifies offset to be
0094         added to PHY refgen RESCODE via IMP_CTRL1 register. It is a PHY
0095         tuning parameter that may vary for different boards of same SOC.
0096       $ref: /schemas/types.yaml#/definitions/uint32
0097       minimum: 0
0098       maximum: 63
0099       default: 0
0100
0101     qcom,bias-ctrl-value:
0102       description:
0103         It is a 6 bit value that specifies bias-ctrl-value. It is a PHY
0104         tuning parameter that may vary for different boards of same SOC.
0105       $ref: /schemas/types.yaml#/definitions/uint32
0106       minimum: 0
0107       maximum: 63
0108       default: 32
0109
0110     qcom,charge-ctrl-value:
0111       description:
0112         It is a 2 bit value that specifies charge-ctrl-value. It is a PHY
0113         tuning parameter that may vary for different boards of same SOC.
0114       $ref: /schemas/types.yaml#/definitions/uint32
0115       minimum: 0
0116       maximum: 3
0117       default: 0
0118
0119     qcom,hstx-trim-value:
0120       description:
0121         It is a 4 bit value that specifies tuning for HSTX
0122         output current.
0123         Possible range is - 15mA to 24mA (stepsize of 600 uA).
0124         See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
0125       $ref: /schemas/types.yaml#/definitions/uint32
0126       minimum: 0
0127       maximum: 15
0128       default: 3
0129
0130     qcom,preemphasis-level:
0131       description:
0132         It is a 2 bit value that specifies pre-emphasis level.
0133         Possible range is 0 to 15% (stepsize of 5%).
0134         See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
0135       $ref: /schemas/types.yaml#/definitions/uint32
0136       minimum: 0
0137       maximum: 3
0138       default: 2
0139
0140     qcom,preemphasis-width:
0141       description:
0142         It is a 1 bit value that specifies how long the HSTX
0143         pre-emphasis (specified using qcom,preemphasis-level) must be in
0144         effect. Duration could be half-bit of full-bit.
0145         See dt-bindings/phy/phy-qcom-qusb2.h for applicable values.
0146       $ref: /schemas/types.yaml#/definitions/uint32
0147       minimum: 0
0148       maximum: 1
0149       default: 0
0150
0151     qcom,hsdisc-trim-value:
0152       description:
0153         It is a 2 bit value tuning parameter that control disconnect
0154         threshold and may vary for different boards of same SOC.
0155       $ref: /schemas/types.yaml#/definitions/uint32
0156       minimum: 0
0157       maximum: 3
0158       default: 0
0159
0160 required:
0161   - compatible
0162   - reg
0163   - "#phy-cells"
0164   - clocks
0165   - clock-names
0166   - vdd-supply
0167   - vdda-pll-supply
0168   - vdda-phy-dpdm-supply
0169   - resets
0170
0171 additionalProperties: false
0172
0173 examples:
0174   - |
0175     #include <dt-bindings/clock/qcom,gcc-msm8996.h>
0176     hsusb_phy: phy@7411000 {
0177         compatible = "qcom,msm8996-qusb2-phy";
0178         reg = <0x7411000 0x180>;
0179         #phy-cells = <0>;
0180
0181         clocks = <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
0182                  <&gcc GCC_RX1_USB2_CLKREF_CLK>;
0183         clock-names = "cfg_ahb", "ref";
0184
0185         vdd-supply = <&pm8994_l28>;
0186         vdda-pll-supply = <&pm8994_l12>;
0187         vdda-phy-dpdm-supply = <&pm8994_l24>;
0188
0189         resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
0190         nvmem-cells = <&qusb2p_hstx_trim>;
0191     };