bindings/phy/qcom%2Cqmp-usb3-dp-phy.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002
0003 %YAML 1.2
0004 ---
0005 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
0006 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0007
0008 title: Qualcomm QMP USB3 DP PHY controller
0009
0010 maintainers:
0011   - Wesley Cheng <quic_wcheng@quicinc.com>
0012
0013 properties:
0014   compatible:
0015     enum:
0016       - qcom,sc7180-qmp-usb3-dp-phy
0017       - qcom,sc7280-qmp-usb3-dp-phy
0018       - qcom,sc8180x-qmp-usb3-dp-phy
0019       - qcom,sdm845-qmp-usb3-dp-phy
0020       - qcom,sm8250-qmp-usb3-dp-phy
0021   reg:
0022     items:
0023       - description: Address and length of PHY's USB serdes block.
0024       - description: Address and length of the DP_COM control block.
0025       - description: Address and length of PHY's DP serdes block.
0026
0027   reg-names:
0028     items:
0029       - const: usb
0030       - const: dp_com
0031       - const: dp
0032
0033   "#clock-cells":
0034     enum: [ 1, 2 ]
0035
0036   "#address-cells":
0037     enum: [ 1, 2 ]
0038
0039   "#size-cells":
0040     enum: [ 1, 2 ]
0041
0042   ranges: true
0043
0044   clocks:
0045     items:
0046       - description: Phy aux clock.
0047       - description: Phy config clock.
0048       - description: 19.2 MHz ref clk.
0049       - description: Phy common block aux clock.
0050
0051   clock-names:
0052     items:
0053       - const: aux
0054       - const: cfg_ahb
0055       - const: ref
0056       - const: com_aux
0057
0058   resets:
0059     items:
0060       - description: reset of phy block.
0061       - description: phy common block reset.
0062
0063   reset-names:
0064     items:
0065       - const: phy
0066       - const: common
0067
0068   vdda-phy-supply:
0069     description:
0070       Phandle to a regulator supply to PHY core block.
0071
0072   vdda-pll-supply:
0073     description:
0074       Phandle to 1.8V regulator supply to PHY refclk pll block.
0075
0076   vddp-ref-clk-supply:
0077     description:
0078       Phandle to a regulator supply to any specific refclk pll block.
0079
0080 #Required nodes:
0081 patternProperties:
0082   "^usb3-phy@[0-9a-f]+$":
0083     type: object
0084     description:
0085       The USB3 PHY.
0086
0087     properties:
0088       reg:
0089         items:
0090           - description: Address and length of TX.
0091           - description: Address and length of RX.
0092           - description: Address and length of PCS.
0093           - description: Address and length of TX2.
0094           - description: Address and length of RX2.
0095           - description: Address and length of pcs_misc.
0096
0097       clocks:
0098         items:
0099           - description: pipe clock
0100
0101       clock-names:
0102         items:
0103           - const: pipe0
0104
0105       clock-output-names:
0106         items:
0107           - const: usb3_phy_pipe_clk_src
0108
0109       '#clock-cells':
0110         const: 0
0111
0112       '#phy-cells':
0113         const: 0
0114
0115     required:
0116       - reg
0117       - clocks
0118       - clock-names
0119       - '#clock-cells'
0120       - '#phy-cells'
0121
0122   "^dp-phy@[0-9a-f]+$":
0123     type: object
0124     description:
0125       The DP PHY.
0126
0127     properties:
0128       reg:
0129         items:
0130           - description: Address and length of TX.
0131           - description: Address and length of RX.
0132           - description: Address and length of PCS.
0133           - description: Address and length of TX2.
0134           - description: Address and length of RX2.
0135
0136       '#clock-cells':
0137         const: 1
0138
0139       '#phy-cells':
0140         const: 0
0141
0142     required:
0143       - reg
0144       - '#clock-cells'
0145       - '#phy-cells'
0146
0147 required:
0148   - compatible
0149   - reg
0150   - "#clock-cells"
0151   - "#address-cells"
0152   - "#size-cells"
0153   - ranges
0154   - clocks
0155   - clock-names
0156   - resets
0157   - reset-names
0158   - vdda-phy-supply
0159   - vdda-pll-supply
0160
0161 additionalProperties: false
0162
0163 examples:
0164   - |
0165     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
0166     usb_1_qmpphy: phy-wrapper@88e9000 {
0167         compatible = "qcom,sdm845-qmp-usb3-dp-phy";
0168         reg = <0x088e9000 0x18c>,
0169               <0x088e8000 0x10>,
0170               <0x088ea000 0x40>;
0171         reg-names = "usb", "dp_com", "dp";
0172         #clock-cells = <1>;
0173         #address-cells = <1>;
0174         #size-cells = <1>;
0175         ranges = <0x0 0x088e9000 0x2000>;
0176
0177         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
0178                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
0179                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
0180                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
0181         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
0182
0183         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
0184                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
0185         reset-names = "phy", "common";
0186
0187         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
0188         vdda-pll-supply = <&vdda_usb2_ss_core>;
0189
0190         usb3-phy@200 {
0191             reg = <0x200 0x128>,
0192                   <0x400 0x200>,
0193                   <0xc00 0x218>,
0194                   <0x600 0x128>,
0195                   <0x800 0x200>,
0196                   <0xa00 0x100>;
0197             #clock-cells = <0>;
0198             #phy-cells = <0>;
0199             clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
0200             clock-names = "pipe0";
0201             clock-output-names = "usb3_phy_pipe_clk_src";
0202         };
0203
0204         dp-phy@88ea200 {
0205             reg = <0xa200 0x200>,
0206                   <0xa400 0x200>,
0207                   <0xaa00 0x200>,
0208                   <0xa600 0x200>,
0209                   <0xa800 0x200>;
0210             #clock-cells = <1>;
0211             #phy-cells = <0>;
0212         };
0213     };