0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/phy/phy-tegra194-p2u.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: NVIDIA Tegra194 & Tegra234 P2U binding
0008
0009 maintainers:
0010 - Thierry Reding <treding@nvidia.com>
0011
0012 description: >
0013 Tegra194 has two PHY bricks namely HSIO (High Speed IO) and NVHS (NVIDIA High
0014 Speed) each interfacing with 12 and 8 P2U instances respectively.
0015 Tegra234 has three PHY bricks namely HSIO, NVHS and GBE (Gigabit Ethernet)
0016 each interfacing with 8, 8 and 8 P2U instances respectively.
0017 A P2U instance is a glue logic between Synopsys DesignWare Core PCIe IP's PIPE
0018 interface and PHY of HSIO/NVHS/GBE bricks. Each P2U instance represents one
0019 PCIe lane.
0020
0021 properties:
0022 compatible:
0023 enum:
0024 - nvidia,tegra194-p2u
0025 - nvidia,tegra234-p2u
0026
0027 reg:
0028 maxItems: 1
0029 description: Should be the physical address space and length of respective each P2U instance.
0030
0031 reg-names:
0032 items:
0033 - const: ctl
0034
0035 nvidia,skip-sz-protect-en:
0036 description: Should be present if two PCIe retimers are present between
0037 the root port and its immediate downstream device.
0038 type: boolean
0039
0040 '#phy-cells':
0041 const: 0
0042
0043 additionalProperties: false
0044
0045 examples:
0046 - |
0047 p2u_hsio_0: phy@3e10000 {
0048 compatible = "nvidia,tegra194-p2u";
0049 reg = <0x03e10000 0x10000>;
0050 reg-names = "ctl";
0051
0052 #phy-cells = <0>;
0053 };
