0001 * ROCKCHIP type-c PHY
0002 ---------------------
0003
0004 Required properties:
0005 - compatible : must be "rockchip,rk3399-typec-phy"
0006 - reg: Address and length of the usb phy control register set
0007 - rockchip,grf : phandle to the syscon managing the "general
0008 register files"
0009 - clocks : phandle + clock specifier for the phy clocks
0010 - clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
0011 - assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
0012 <&cru SCLK_UPHY1_TCPDCORE>;
0013 - assigned-clock-rates : the phy core clk frequency, shall be: 50000000
0014 - resets : a list of phandle + reset specifier pairs
0015 - reset-names : string reset name, must be:
0016 "uphy", "uphy-pipe", "uphy-tcphy"
0017
0018 Optional properties:
0019 - extcon : extcon specifier for the Power Delivery
0020
0021 Required nodes : a sub-node is required for each port the phy provides.
0022 The sub-node name is used to identify dp or usb3 port,
0023 and shall be the following entries:
0024 * "dp-port" : the name of DP port.
0025 * "usb3-port" : the name of USB3 port.
0026
0027 Required properties (port (child) node):
0028 - #phy-cells : must be 0, See ./phy-bindings.txt for details.
0029
0030 Deprecated properties, do not use in new device tree sources, these
0031 properties are determined by the compatible value:
0032 - rockchip,typec-conn-dir
0033 - rockchip,usb3tousb2-en
0034 - rockchip,external-psm
0035 - rockchip,pipe-status
0036
0037 Example:
0038 tcphy0: phy@ff7c0000 {
0039 compatible = "rockchip,rk3399-typec-phy";
0040 reg = <0x0 0xff7c0000 0x0 0x40000>;
0041 rockchip,grf = <&grf>;
0042 extcon = <&fusb0>;
0043 clocks = <&cru SCLK_UPHY0_TCPDCORE>,
0044 <&cru SCLK_UPHY0_TCPDPHY_REF>;
0045 clock-names = "tcpdcore", "tcpdphy-ref";
0046 assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
0047 assigned-clock-rates = <50000000>;
0048 resets = <&cru SRST_UPHY0>,
0049 <&cru SRST_UPHY0_PIPE_L00>,
0050 <&cru SRST_P_UPHY0_TCPHY>;
0051 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
0052
0053 tcphy0_dp: dp-port {
0054 #phy-cells = <0>;
0055 };
0056
0057 tcphy0_usb3: usb3-port {
0058 #phy-cells = <0>;
0059 };
0060 };
0061
0062 tcphy1: phy@ff800000 {
0063 compatible = "rockchip,rk3399-typec-phy";
0064 reg = <0x0 0xff800000 0x0 0x40000>;
0065 rockchip,grf = <&grf>;
0066 extcon = <&fusb1>;
0067 clocks = <&cru SCLK_UPHY1_TCPDCORE>,
0068 <&cru SCLK_UPHY1_TCPDPHY_REF>;
0069 clock-names = "tcpdcore", "tcpdphy-ref";
0070 assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
0071 assigned-clock-rates = <50000000>;
0072 resets = <&cru SRST_UPHY1>,
0073 <&cru SRST_UPHY1_PIPE_L00>,
0074 <&cru SRST_P_UPHY1_TCPHY>;
0075 reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
0076
0077 tcphy1_dp: dp-port {
0078 #phy-cells = <0>;
0079 };
0080
0081 tcphy1_usb3: usb3-port {
0082 #phy-cells = <0>;
0083 };
0084 };
