bindings/phy/phy-rockchip-naneng-combphy.yaml

0001 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: http://devicetree.org/schemas/phy/phy-rockchip-naneng-combphy.yaml#
0005 $schema: http://devicetree.org/meta-schemas/core.yaml#
0006
0007 title: Rockchip SoC Naneng Combo Phy Device Tree Bindings
0008
0009 maintainers:
0010   - Heiko Stuebner <heiko@sntech.de>
0011
0012 properties:
0013   compatible:
0014     enum:
0015       - rockchip,rk3568-naneng-combphy
0016
0017   reg:
0018     maxItems: 1
0019
0020   clocks:
0021     items:
0022       - description: reference clock
0023       - description: apb clock
0024       - description: pipe clock
0025
0026   clock-names:
0027     items:
0028       - const: ref
0029       - const: apb
0030       - const: pipe
0031
0032   resets:
0033     items:
0034       - description: exclusive PHY reset line
0035
0036   rockchip,enable-ssc:
0037     type: boolean
0038     description:
0039       The option SSC can be enabled for U3, SATA and PCIE.
0040       Most commercially available platforms use SSC to reduce EMI.
0041
0042   rockchip,ext-refclk:
0043     type: boolean
0044     description:
0045       Many PCIe connections, especially backplane connections,
0046       require a synchronous reference clock between the two link partners.
0047       To achieve this a common clock source, referred to as REFCLK in
0048       the PCI Express Card Electromechanical Specification,
0049       should be used by both ends of the PCIe link.
0050       In PCIe mode one can choose to use an internal or an external reference
0051       clock.
0052       By default the internal clock is selected. The PCIe PHY provides a 100MHz
0053       differential clock output(optional with SSC) for system applications.
0054       When selecting this option an externally 100MHz differential
0055       reference clock needs to be provided to the PCIe PHY.
0056
0057   rockchip,pipe-grf:
0058     $ref: /schemas/types.yaml#/definitions/phandle
0059     description:
0060       Some additional phy settings are accessed through GRF regs.
0061
0062   rockchip,pipe-phy-grf:
0063     $ref: /schemas/types.yaml#/definitions/phandle
0064     description:
0065       Some additional pipe settings are accessed through GRF regs.
0066
0067   "#phy-cells":
0068     const: 1
0069
0070 required:
0071   - compatible
0072   - reg
0073   - clocks
0074   - clock-names
0075   - resets
0076   - rockchip,pipe-grf
0077   - rockchip,pipe-phy-grf
0078   - "#phy-cells"
0079
0080 additionalProperties: false
0081
0082 examples:
0083   - |
0084     #include <dt-bindings/clock/rk3568-cru.h>
0085
0086     pipegrf: syscon@fdc50000 {
0087       compatible = "rockchip,rk3568-pipe-grf", "syscon";
0088       reg = <0xfdc50000 0x1000>;
0089     };
0090
0091     pipe_phy_grf0: syscon@fdc70000 {
0092       compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
0093       reg = <0xfdc70000 0x1000>;
0094     };
0095
0096     combphy0: phy@fe820000 {
0097       compatible = "rockchip,rk3568-naneng-combphy";
0098       reg = <0xfe820000 0x100>;
0099       clocks = <&pmucru CLK_PCIEPHY0_REF>,
0100                <&cru PCLK_PIPEPHY0>,
0101                <&cru PCLK_PIPE>;
0102       clock-names = "ref", "apb", "pipe";
0103       assigned-clocks = <&pmucru CLK_PCIEPHY0_REF>;
0104       assigned-clock-rates = <100000000>;
0105       resets = <&cru SRST_PIPEPHY0>;
0106       rockchip,pipe-grf = <&pipegrf>;
0107       rockchip,pipe-phy-grf = <&pipe_phy_grf0>;
0108       #phy-cells = <1>;
0109     };