0001 ROCKCHIP HDMI PHY WITH INNO IP BLOCK
0002
0003 Required properties:
0004 - compatible : should be one of the listed compatibles:
0005 * "rockchip,rk3228-hdmi-phy",
0006 * "rockchip,rk3328-hdmi-phy";
0007 - reg : Address and length of the hdmi phy control register set
0008 - clocks : phandle + clock specifier for the phy clocks
0009 - clock-names : string, clock name, must contain "sysclk" for system
0010 control and register configuration, "refoclk" for crystal-
0011 oscillator reference PLL clock input and "refpclk" for pclk-
0012 based refeference PLL clock input.
0013 - #clock-cells: should be 0.
0014 - clock-output-names : shall be the name for the output clock.
0015 - interrupts : phandle + interrupt specified for the hdmiphy interrupt
0016 - #phy-cells : must be 0. See ./phy-bindings.txt for details.
0017
0018 Optional properties for rk3328-hdmi-phy:
0019 - nvmem-cells = phandle + nvmem specifier for the cpu-version efuse
0020 - nvmem-cell-names : "cpu-version" to read the chip version, required
0021 for adjustment to some frequency settings
0022
0023 Example:
0024 hdmi_phy: hdmi-phy@12030000 {
0025 compatible = "rockchip,rk3228-hdmi-phy";
0026 reg = <0x12030000 0x10000>;
0027 #phy-cells = <0>;
0028 clocks = <&cru PCLK_HDMI_PHY>, <&xin24m>, <&cru DCLK_HDMIPHY>;
0029 clock-names = "sysclk", "refoclk", "refpclk";
0030 #clock-cells = <0>;
0031 clock-output-names = "hdmi_phy";
0032 status = "disabled";
0033 };
0034
0035 Then the PHY can be used in other nodes such as:
0036
0037 hdmi: hdmi@200a0000 {
0038 compatible = "rockchip,rk3228-dw-hdmi";
0039 ...
0040 phys = <&hdmi_phy>;
0041 phy-names = "hdmi";
0042 ...
0043 };
