0001 Microsemi Ocelot SerDes muxing driver
0002 -------------------------------------
0003
0004 On Microsemi Ocelot, there is a handful of registers in HSIO address
0005 space for setting up the SerDes to switch port muxing.
0006
0007 A SerDes X can be "muxed" to work with switch port Y or Z for example.
0008 One specific SerDes can also be used as a PCIe interface.
0009
0010 Hence, a SerDes represents an interface, be it an Ethernet or a PCIe one.
0011
0012 There are two kinds of SerDes: SERDES1G supports 10/100Mbps in
0013 half/full-duplex and 1000Mbps in full-duplex mode while SERDES6G supports
0014 10/100Mbps in half/full-duplex and 1000/2500Mbps in full-duplex mode.
0015
0016 Also, SERDES6G number (aka "macro") 0 is the only interface supporting
0017 QSGMII.
0018
0019 This is a child of the HSIO syscon ("mscc,ocelot-hsio", see
0020 Documentation/devicetree/bindings/mips/mscc.txt) on the Microsemi Ocelot.
0021
0022 Required properties:
0023
0024 - compatible: should be "mscc,vsc7514-serdes"
0025 - #phy-cells : from the generic phy bindings, must be 2.
0026 The first number defines the input port to use for a given
0027 SerDes macro. The second defines the macro to use. They are
0028 defined in dt-bindings/phy/phy-ocelot-serdes.h
0029
0030 Example:
0031
0032 serdes: serdes {
0033 compatible = "mscc,vsc7514-serdes";
0034 #phy-cells = <2>;
0035 };
0036
0037 ethernet {
0038 port1 {
0039 phy-handle = <&phy_foo>;
0040 /* Link SERDES1G_5 to port1 */
0041 phys = <&serdes 1 SERDES1G_5>;
0042 };
0043 };
