0001 MVEBU comphy drivers
0002 --------------------
0003
0004 COMPHY controllers can be found on the following Marvell MVEBU SoCs:
0005 * Armada 7k/8k (on the CP110)
0006 * Armada 3700
0007 It provides a number of shared PHYs used by various interfaces (network, SATA,
0008 USB, PCIe...).
0009
0010 Required properties:
0011
0012 - compatible: should be one of:
0013 * "marvell,comphy-cp110" for Armada 7k/8k
0014 * "marvell,comphy-a3700" for Armada 3700
0015 - reg: should contain the COMPHY register(s) location(s) and length(s).
0016 * 1 entry for Armada 7k/8k
0017 * 4 entries for Armada 3700 along with the corresponding reg-names
0018 properties, memory areas are:
0019 * Generic COMPHY registers
0020 * Lane 1 (PCIe/GbE)
0021 * Lane 0 (USB3/GbE)
0022 * Lane 2 (SATA/USB3)
0023 - marvell,system-controller: should contain a phandle to the system
0024 controller node (only for Armada 7k/8k)
0025 - #address-cells: should be 1.
0026 - #size-cells: should be 0.
0027
0028 Optional properlties:
0029
0030 - clocks: pointers to the reference clocks for this device (CP110 only),
0031 consequently: MG clock, MG Core clock, AXI clock.
0032 - clock-names: names of used clocks for CP110 only, must be :
0033 "mg_clk", "mg_core_clk" and "axi_clk".
0034
0035 A sub-node is required for each comphy lane provided by the comphy.
0036
0037 Required properties (child nodes):
0038
0039 - reg: COMPHY lane number.
0040 - #phy-cells : from the generic PHY bindings, must be 1. Defines the
0041 input port to use for a given comphy lane.
0042
0043 Examples:
0044
0045 CP11X_LABEL(comphy): phy@120000 {
0046 compatible = "marvell,comphy-cp110";
0047 reg = <0x120000 0x6000>;
0048 marvell,system-controller = <&CP11X_LABEL(syscon0)>;
0049 clocks = <&CP11X_LABEL(clk) 1 5>, <&CP11X_LABEL(clk) 1 6>,
0050 <&CP11X_LABEL(clk) 1 18>;
0051 clock-names = "mg_clk", "mg_core_clk", "axi_clk";
0052 #address-cells = <1>;
0053 #size-cells = <0>;
0054
0055 CP11X_LABEL(comphy0): phy@0 {
0056 reg = <0>;
0057 #phy-cells = <1>;
0058 };
0059
0060 CP11X_LABEL(comphy1): phy@1 {
0061 reg = <1>;
0062 #phy-cells = <1>;
0063 };
0064 };
0065
0066 comphy: phy@18300 {
0067 compatible = "marvell,comphy-a3700";
0068 reg = <0x18300 0x300>,
0069 <0x1F000 0x400>,
0070 <0x5C000 0x400>,
0071 <0xe0178 0x8>;
0072 reg-names = "comphy",
0073 "lane1_pcie_gbe",
0074 "lane0_usb3_gbe",
0075 "lane2_sata_usb3";
0076 #address-cells = <1>;
0077 #size-cells = <0>;
0078
0079
0080 comphy0: phy@0 {
0081 reg = <0>;
0082 #phy-cells = <1>;
0083 };
0084
0085 comphy1: phy@1 {
0086 reg = <1>;
0087 #phy-cells = <1>;
0088 };
0089
0090 comphy2: phy@2 {
0091 reg = <2>;
0092 #phy-cells = <1>;
0093 };
0094 };
