0001 STMicroelectronics STi MIPHY365x PHY binding
0002 ============================================
0003
0004 This binding describes a miphy device that is used to control PHY hardware
0005 for SATA and PCIe.
0006
0007 Required properties (controller (parent) node):
0008 - compatible : Should be "st,miphy365x-phy"
0009 - st,syscfg : Phandle / integer array property. Phandle of sysconfig group
0010 containing the miphy registers and integer array should contain
0011 an entry for each port sub-node, specifying the control
0012 register offset inside the sysconfig group.
0013
0014 Required nodes : A sub-node is required for each channel the controller
0015 provides. Address range information including the usual
0016 'reg' and 'reg-names' properties are used inside these
0017 nodes to describe the controller's topology. These nodes
0018 are translated by the driver's .xlate() function.
0019
0020 Required properties (port (child) node):
0021 - #phy-cells : Should be 1 (See second example)
0022 Cell after port phandle is device type from:
0023 - PHY_TYPE_SATA
0024 - PHY_TYPE_PCI
0025 - reg : Address and length of register sets for each device in
0026 "reg-names"
0027 - reg-names : The names of the register addresses corresponding to the
0028 registers filled in "reg":
0029 - sata: For SATA devices
0030 - pcie: For PCIe devices
0031
0032 Optional properties (port (child) node):
0033 - st,sata-gen : Generation of locally attached SATA IP. Expected values
0034 are {1,2,3). If not supplied generation 1 hardware will
0035 be expected
0036 - st,pcie-tx-pol-inv : Bool property to invert the polarity PCIe Tx (Txn/Txp)
0037 - st,sata-tx-pol-inv : Bool property to invert the polarity SATA Tx (Txn/Txp)
0038
0039 Example:
0040
0041 miphy365x_phy: miphy365x@fe382000 {
0042 compatible = "st,miphy365x-phy";
0043 st,syscfg = <&syscfg_rear 0x824 0x828>;
0044 #address-cells = <1>;
0045 #size-cells = <1>;
0046 ranges;
0047
0048 phy_port0: port@fe382000 {
0049 reg = <0xfe382000 0x100>, <0xfe394000 0x100>;
0050 reg-names = "sata", "pcie";
0051 #phy-cells = <1>;
0052 st,sata-gen = <3>;
0053 };
0054
0055 phy_port1: port@fe38a000 {
0056 reg = <0xfe38a000 0x100>, <0xfe804000 0x100>;;
0057 reg-names = "sata", "pcie", "syscfg";
0058 #phy-cells = <1>;
0059 st,pcie-tx-pol-inv;
0060 };
0061 };
0062
0063 Specifying phy control of devices
0064 =================================
0065
0066 Device nodes should specify the configuration required in their "phys"
0067 property, containing a phandle to the phy port node and a device type.
0068
0069 Example:
0070
0071 #include <dt-bindings/phy/phy.h>
0072
0073 sata0: sata@fe380000 {
0074 ...
0075 phys = <&phy_port0 PHY_TYPE_SATA>;
0076 ...
0077 };
