0001 STMicroelectronics STi MIPHY28LP PHY binding
0002 ============================================
0003
0004 This binding describes a miphy device that is used to control PHY hardware
0005 for SATA, PCIe or USB3.
0006
0007 Required properties (controller (parent) node):
0008 - compatible : Should be "st,miphy28lp-phy".
0009 - st,syscfg : Should be a phandle of the system configuration register group
0010 which contain the SATA, PCIe or USB3 mode setting bits.
0011
0012 Required nodes : A sub-node is required for each channel the controller
0013 provides. Address range information including the usual
0014 'reg' and 'reg-names' properties are used inside these
0015 nodes to describe the controller's topology. These nodes
0016 are translated by the driver's .xlate() function.
0017
0018 Required properties (port (child) node):
0019 - #phy-cells : Should be 1 (See second example)
0020 Cell after port phandle is device type from:
0021 - PHY_TYPE_SATA
0022 - PHY_TYPE_PCI
0023 - PHY_TYPE_USB3
0024 - reg : Address and length of the register set for the device.
0025 - reg-names : The names of the register addresses corresponding to the registers
0026 filled in "reg". It can also contain the offset of the system configuration
0027 registers used as glue-logic to setup the device for SATA/PCIe or USB3
0028 devices.
0029 - st,syscfg : Offset of the parent configuration register.
0030 - resets : phandle to the parent reset controller.
0031 - reset-names : Associated name must be "miphy-sw-rst".
0032
0033 Optional properties (port (child) node):
0034 - st,osc-rdy : to check the MIPHY0_OSC_RDY status in the glue-logic. This
0035 is not available in all the MiPHY. For example, for STiH407, only the
0036 MiPHY0 has this bit.
0037 - st,osc-force-ext : to select the external oscillator. This can change from
0038 different MiPHY inside the same SoC.
0039 - st,sata_gen : to select which SATA_SPDMODE has to be set in the SATA system config
0040 register.
0041 - st,px_rx_pol_inv : to invert polarity of RXn/RXp (respectively negative line and positive
0042 line).
0043 - st,scc-on : enable ssc to reduce effects of EMI (only for sata or PCIe).
0044 - st,tx-impedance-comp : to compensate tx impedance avoiding out of range values.
0045
0046 example:
0047
0048 miphy28lp_phy: miphy28lp@9b22000 {
0049 compatible = "st,miphy28lp-phy";
0050 st,syscfg = <&syscfg_core>;
0051 #address-cells = <1>;
0052 #size-cells = <1>;
0053 ranges;
0054
0055 phy_port0: port@9b22000 {
0056 reg = <0x9b22000 0xff>,
0057 <0x9b09000 0xff>,
0058 <0x9b04000 0xff>;
0059 reg-names = "sata-up",
0060 "pcie-up",
0061 "pipew";
0062
0063 st,syscfg = <0x114 0x818 0xe0 0xec>;
0064 #phy-cells = <1>;
0065 st,osc-rdy;
0066 reset-names = "miphy-sw-rst";
0067 resets = <&softreset STIH407_MIPHY0_SOFTRESET>;
0068 };
0069
0070 phy_port1: port@9b2a000 {
0071 reg = <0x9b2a000 0xff>,
0072 <0x9b19000 0xff>,
0073 <0x9b14000 0xff>;
0074 reg-names = "sata-up",
0075 "pcie-up",
0076 "pipew";
0077
0078 st,syscfg = <0x118 0x81c 0xe4 0xf0>;
0079
0080 #phy-cells = <1>;
0081 st,osc-force-ext;
0082 reset-names = "miphy-sw-rst";
0083 resets = <&softreset STIH407_MIPHY1_SOFTRESET>;
0084 };
0085
0086 phy_port2: port@8f95000 {
0087 reg = <0x8f95000 0xff>,
0088 <0x8f90000 0xff>;
0089 reg-names = "pipew",
0090 "usb3-up";
0091
0092 st,syscfg = <0x11c 0x820>;
0093
0094 #phy-cells = <1>;
0095 reset-names = "miphy-sw-rst";
0096 resets = <&softreset STIH407_MIPHY2_SOFTRESET>;
0097 };
0098 };
0099
0100
0101 Specifying phy control of devices
0102 =================================
0103
0104 Device nodes should specify the configuration required in their "phys"
0105 property, containing a phandle to the miphy device node and an index
0106 specifying which configuration to use, as described in phy-bindings.txt.
0107
0108 example:
0109 sata0: sata@9b20000 {
0110 ...
0111 phys = <&phy_port0 PHY_TYPE_SATA>;
0112 ...
0113 };
0114
0115 Macro definitions for the supported miphy configuration can be found in:
0116
0117 include/dt-bindings/phy/phy.h
