Back to home page

OSCL-LXR

 
 

    


0001 Lantiq XWAY SoC RCU USB 1.1/2.0 PHY binding
0002 ===========================================
0003 
0004 This binding describes the USB PHY hardware provided by the RCU module on the
0005 Lantiq XWAY SoCs.
0006 
0007 This node has to be a sub node of the Lantiq RCU block.
0008 
0009 -------------------------------------------------------------------------------
0010 Required properties (controller (parent) node):
0011 - compatible    : Should be one of
0012                         "lantiq,ase-usb2-phy"
0013                         "lantiq,danube-usb2-phy"
0014                         "lantiq,xrx100-usb2-phy"
0015                         "lantiq,xrx200-usb2-phy"
0016                         "lantiq,xrx300-usb2-phy"
0017 - reg           : Defines the following sets of registers in the parent
0018                   syscon device
0019                         - Offset of the USB PHY configuration register
0020                         - Offset of the USB Analog configuration
0021                           register (only for xrx200 and xrx200)
0022 - clocks        : References to the (PMU) "phy" clk gate.
0023 - clock-names   : Must be "phy"
0024 - resets        : References to the RCU USB configuration reset bits.
0025 - reset-names   : Must be one of the following:
0026                         "phy" (optional)
0027                         "ctrl" (shared)
0028 
0029 -------------------------------------------------------------------------------
0030 Example for the USB PHYs on an xRX200 SoC:
0031         usb_phy0: usb2-phy@18 {
0032                 compatible = "lantiq,xrx200-usb2-phy";
0033                 reg = <0x18 4>, <0x38 4>;
0034 
0035                 clocks = <&pmu PMU_GATE_USB0_PHY>;
0036                 clock-names = "phy";
0037                 resets = <&reset1 4 4>, <&reset0 4 4>;
0038                 reset-names = "phy", "ctrl";
0039                 #phy-cells = <0>;
0040         };