0001 Device tree bindings for HiSilicon INNO USB2 PHY
0002
0003 Required properties:
0004 - compatible: Should be one of the following strings:
0005 "hisilicon,inno-usb2-phy",
0006 "hisilicon,hi3798cv200-usb2-phy".
0007 - reg: Should be the address space for PHY configuration register in peripheral
0008 controller, e.g. PERI_USB0 for USB 2.0 PHY01 on Hi3798CV200 SoC.
0009 - clocks: The phandle and clock specifier pair for INNO USB2 PHY device
0010 reference clock.
0011 - resets: The phandle and reset specifier pair for INNO USB2 PHY device reset
0012 signal.
0013 - #address-cells: Must be 1.
0014 - #size-cells: Must be 0.
0015
0016 The INNO USB2 PHY device should be a child node of peripheral controller that
0017 contains the PHY configuration register, and each device suppports up to 2 PHY
0018 ports which are represented as child nodes of INNO USB2 PHY device.
0019
0020 Required properties for PHY port node:
0021 - reg: The PHY port instance number.
0022 - #phy-cells: Defined by generic PHY bindings. Must be 0.
0023 - resets: The phandle and reset specifier pair for PHY port reset signal.
0024
0025 Refer to phy/phy-bindings.txt for the generic PHY binding properties
0026
0027 Example:
0028
0029 perictrl: peripheral-controller@8a20000 {
0030 compatible = "hisilicon,hi3798cv200-perictrl", "simple-mfd";
0031 reg = <0x8a20000 0x1000>;
0032 #address-cells = <1>;
0033 #size-cells = <1>;
0034 ranges = <0x0 0x8a20000 0x1000>;
0035
0036 usb2_phy1: usb2-phy@120 {
0037 compatible = "hisilicon,hi3798cv200-usb2-phy";
0038 reg = <0x120 0x4>;
0039 clocks = <&crg HISTB_USB2_PHY1_REF_CLK>;
0040 resets = <&crg 0xbc 4>;
0041 #address-cells = <1>;
0042 #size-cells = <0>;
0043
0044 usb2_phy1_port0: phy@0 {
0045 reg = <0>;
0046 #phy-cells = <0>;
0047 resets = <&crg 0xbc 8>;
0048 };
0049
0050 usb2_phy1_port1: phy@1 {
0051 reg = <1>;
0052 #phy-cells = <0>;
0053 resets = <&crg 0xbc 9>;
0054 };
0055 };
0056
0057 usb2_phy2: usb2-phy@124 {
0058 compatible = "hisilicon,hi3798cv200-usb2-phy";
0059 reg = <0x124 0x4>;
0060 clocks = <&crg HISTB_USB2_PHY2_REF_CLK>;
0061 resets = <&crg 0xbc 6>;
0062 #address-cells = <1>;
0063 #size-cells = <0>;
0064
0065 usb2_phy2_port0: phy@0 {
0066 reg = <0>;
0067 #phy-cells = <0>;
0068 resets = <&crg 0xbc 10>;
0069 };
0070 };
0071 };
