0001 HiSilicon STB PCIE/SATA/USB3 PHY
0002
0003 Required properties:
0004 - compatible: Should be "hisilicon,hi3798cv200-combphy"
0005 - reg: Should be the address space for COMBPHY configuration and state
0006 registers in peripheral controller, e.g. PERI_COMBPHY0_CFG and
0007 PERI_COMBPHY0_STATE for COMBPHY0 Hi3798CV200 SoC.
0008 - #phy-cells: Should be 1. The cell number is used to select the phy mode
0009 as defined in <dt-bindings/phy/phy.h>.
0010 - clocks: The phandle to clock provider and clock specifier pair.
0011 - resets: The phandle to reset controller and reset specifier pair.
0012
0013 Refer to phy/phy-bindings.txt for the generic PHY binding properties.
0014
0015 Optional properties:
0016 - hisilicon,fixed-mode: If the phy device doesn't support mode select
0017 but a fixed mode setting, the property should be present to specify
0018 the particular mode.
0019 - hisilicon,mode-select-bits: If the phy device support mode select,
0020 this property should be present to specify the register bits in
0021 peripheral controller, as a 3 integers tuple:
0022 <register_offset bit_shift bit_mask>.
0023
0024 Notes:
0025 - Between hisilicon,fixed-mode and hisilicon,mode-select-bits, one and only
0026 one of them should be present.
0027 - The device node should be a child of peripheral controller that contains
0028 COMBPHY configuration/state and PERI_CTRL register used to select PHY mode.
0029 Refer to arm/hisilicon/hisilicon.txt for the parent peripheral controller
0030 bindings.
0031
0032 Examples:
0033
0034 perictrl: peripheral-controller@8a20000 {
0035 compatible = "hisilicon,hi3798cv200-perictrl", "syscon",
0036 "simple-mfd";
0037 reg = <0x8a20000 0x1000>;
0038 #address-cells = <1>;
0039 #size-cells = <1>;
0040 ranges = <0x0 0x8a20000 0x1000>;
0041
0042 combphy0: phy@850 {
0043 compatible = "hisilicon,hi3798cv200-combphy";
0044 reg = <0x850 0x8>;
0045 #phy-cells = <1>;
0046 clocks = <&crg HISTB_COMBPHY0_CLK>;
0047 resets = <&crg 0x188 4>;
0048 hisilicon,fixed-mode = <PHY_TYPE_USB3>;
0049 };
0050
0051 combphy1: phy@858 {
0052 compatible = "hisilicon,hi3798cv200-combphy";
0053 reg = <0x858 0x8>;
0054 #phy-cells = <1>;
0055 clocks = <&crg HISTB_COMBPHY1_CLK>;
0056 resets = <&crg 0x188 12>;
0057 hisilicon,mode-select-bits = <0x0008 11 (0x3 << 11)>;
0058 };
0059 };
