0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Cadence Torrent SD0801 PHY binding
0008
0009 description:
0010 This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
0011 hardware included with the Cadence MHDP DisplayPort controller. Torrent
0012 PHY also supports multilink multiprotocol combinations including protocols
0013 such as PCIe, USB, SGMII, QSGMII etc.
0014
0015 maintainers:
0016 - Swapnil Jakhade <sjakhade@cadence.com>
0017 - Yuti Amonkar <yamonkar@cadence.com>
0018
0019 properties:
0020 compatible:
0021 enum:
0022 - cdns,torrent-phy
0023 - ti,j721e-serdes-10g
0024
0025 '#address-cells':
0026 const: 1
0027
0028 '#size-cells':
0029 const: 0
0030
0031 '#clock-cells':
0032 const: 1
0033
0034 clocks:
0035 minItems: 1
0036 maxItems: 2
0037 description:
0038 PHY reference clock for 1 item. Must contain an entry in clock-names.
0039 Optional Parent to enable output reference clock.
0040
0041 clock-names:
0042 minItems: 1
0043 items:
0044 - const: refclk
0045 - const: phy_en_refclk
0046
0047 assigned-clocks:
0048 maxItems: 3
0049
0050 assigned-clock-parents:
0051 maxItems: 3
0052
0053 reg:
0054 minItems: 1
0055 items:
0056 - description: Offset of the Torrent PHY configuration registers.
0057 - description: Offset of the DPTX PHY configuration registers.
0058
0059 reg-names:
0060 minItems: 1
0061 items:
0062 - const: torrent_phy
0063 - const: dptx_phy
0064
0065 resets:
0066 minItems: 1
0067 items:
0068 - description: Torrent PHY reset.
0069 - description: Torrent APB reset. This is optional.
0070
0071 reset-names:
0072 minItems: 1
0073 items:
0074 - const: torrent_reset
0075 - const: torrent_apb
0076
0077 patternProperties:
0078 '^phy@[0-3]$':
0079 type: object
0080 description:
0081 Each group of PHY lanes with a single master lane should be represented as a sub-node.
0082 properties:
0083 reg:
0084 description:
0085 The master lane number. This is the lowest numbered lane in the lane group.
0086 minimum: 0
0087 maximum: 3
0088
0089 resets:
0090 minItems: 1
0091 maxItems: 4
0092 description:
0093 Contains list of resets, one per lane, to get all the link lanes out of reset.
0094
0095 "#phy-cells":
0096 const: 0
0097
0098 cdns,phy-type:
0099 description:
0100 Specifies the type of PHY for which the group of PHY lanes is used.
0101 Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
0102 $ref: /schemas/types.yaml#/definitions/uint32
0103 minimum: 1
0104 maximum: 9
0105
0106 cdns,num-lanes:
0107 description:
0108 Number of lanes.
0109 $ref: /schemas/types.yaml#/definitions/uint32
0110 enum: [1, 2, 3, 4]
0111 default: 4
0112
0113 cdns,ssc-mode:
0114 description:
0115 Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
0116 EXTERNAL_SSC or INTERNAL_SSC.
0117 Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
0118 $ref: /schemas/types.yaml#/definitions/uint32
0119 enum: [0, 1, 2]
0120 default: 0
0121
0122 cdns,max-bit-rate:
0123 description:
0124 Maximum DisplayPort link bit rate to use, in Mbps
0125 $ref: /schemas/types.yaml#/definitions/uint32
0126 enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
0127 default: 8100
0128
0129 required:
0130 - reg
0131 - resets
0132 - "#phy-cells"
0133 - cdns,phy-type
0134 - cdns,num-lanes
0135
0136 additionalProperties: false
0137
0138 required:
0139 - compatible
0140 - "#address-cells"
0141 - "#size-cells"
0142 - clocks
0143 - clock-names
0144 - reg
0145 - reg-names
0146 - resets
0147 - reset-names
0148
0149 additionalProperties: false
0150
0151 examples:
0152 - |
0153 #include <dt-bindings/phy/phy.h>
0154
0155 bus {
0156 #address-cells = <2>;
0157 #size-cells = <2>;
0158
0159 torrent-phy@f0fb500000 {
0160 compatible = "cdns,torrent-phy";
0161 reg = <0xf0 0xfb500000 0x0 0x00100000>,
0162 <0xf0 0xfb030a00 0x0 0x00000040>;
0163 reg-names = "torrent_phy", "dptx_phy";
0164 resets = <&phyrst 0>;
0165 reset-names = "torrent_reset";
0166 clocks = <&ref_clk>;
0167 clock-names = "refclk";
0168 #address-cells = <1>;
0169 #size-cells = <0>;
0170 phy@0 {
0171 reg = <0>;
0172 resets = <&phyrst 1>, <&phyrst 2>,
0173 <&phyrst 3>, <&phyrst 4>;
0174 #phy-cells = <0>;
0175 cdns,phy-type = <PHY_TYPE_DP>;
0176 cdns,num-lanes = <4>;
0177 cdns,max-bit-rate = <8100>;
0178 };
0179 };
0180 };
0181 - |
0182 #include <dt-bindings/phy/phy.h>
0183 #include <dt-bindings/phy/phy-cadence.h>
0184
0185 bus {
0186 #address-cells = <2>;
0187 #size-cells = <2>;
0188
0189 torrent-phy@f0fb500000 {
0190 compatible = "cdns,torrent-phy";
0191 reg = <0xf0 0xfb500000 0x0 0x00100000>;
0192 reg-names = "torrent_phy";
0193 resets = <&phyrst 0>, <&phyrst 1>;
0194 reset-names = "torrent_reset", "torrent_apb";
0195 clocks = <&ref_clk>;
0196 clock-names = "refclk";
0197 #address-cells = <1>;
0198 #size-cells = <0>;
0199 phy@0 {
0200 reg = <0>;
0201 resets = <&phyrst 2>, <&phyrst 3>;
0202 #phy-cells = <0>;
0203 cdns,phy-type = <PHY_TYPE_PCIE>;
0204 cdns,num-lanes = <2>;
0205 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
0206 };
0207
0208 phy@2 {
0209 reg = <2>;
0210 resets = <&phyrst 4>;
0211 #phy-cells = <0>;
0212 cdns,phy-type = <PHY_TYPE_SGMII>;
0213 cdns,num-lanes = <1>;
0214 cdns,ssc-mode = <CDNS_SERDES_NO_SSC>;
0215 };
0216 };
0217 };
0218 ...
