bindings/phy/phy-cadence-sierra.yaml

0001 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
0002 %YAML 1.2
0003 ---
0004 $id: "http://devicetree.org/schemas/phy/phy-cadence-sierra.yaml#"
0005 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
0006
0007 title: Cadence Sierra PHY binding
0008
0009 description:
0010   This binding describes the Cadence Sierra PHY. Sierra PHY supports multilink
0011   multiprotocol combinations including protocols such as PCIe, USB etc.
0012
0013 maintainers:
0014   - Swapnil Jakhade <sjakhade@cadence.com>
0015   - Yuti Amonkar <yamonkar@cadence.com>
0016
0017 properties:
0018   compatible:
0019     enum:
0020       - cdns,sierra-phy-t0
0021       - ti,sierra-phy-t0
0022
0023   '#address-cells':
0024     const: 1
0025
0026   '#size-cells':
0027     const: 0
0028
0029   '#clock-cells':
0030     const: 1
0031
0032   resets:
0033     minItems: 1
0034     items:
0035       - description: Sierra PHY reset.
0036       - description: Sierra APB reset. This is optional.
0037
0038   reset-names:
0039     minItems: 1
0040     items:
0041       - const: sierra_reset
0042       - const: sierra_apb
0043
0044   reg:
0045     maxItems: 1
0046     description:
0047       Offset of the Sierra PHY configuration registers.
0048
0049   reg-names:
0050     const: serdes
0051
0052   clocks:
0053     minItems: 2
0054     maxItems: 4
0055
0056   clock-names:
0057     minItems: 2
0058     items:
0059       - const: cmn_refclk_dig_div
0060       - const: cmn_refclk1_dig_div
0061       - const: pll0_refclk
0062       - const: pll1_refclk
0063
0064   assigned-clocks:
0065     minItems: 1
0066     maxItems: 2
0067
0068   assigned-clock-parents:
0069     minItems: 1
0070     maxItems: 2
0071
0072   cdns,autoconf:
0073     type: boolean
0074     description:
0075       A boolean property whose presence indicates that the PHY registers will be
0076       configured by hardware. If not present, all sub-node optional properties
0077       must be provided.
0078
0079 patternProperties:
0080   '^phy@[0-9a-f]$':
0081     type: object
0082     description:
0083       Each group of PHY lanes with a single master lane should be represented as
0084       a sub-node. Note that the actual configuration of each lane is determined
0085       by hardware strapping, and must match the configuration specified here.
0086     properties:
0087       reg:
0088         description:
0089           The master lane number. This is the lowest numbered lane in the lane group.
0090         minimum: 0
0091         maximum: 15
0092
0093       resets:
0094         minItems: 1
0095         maxItems: 4
0096         description:
0097           Contains list of resets, one per lane, to get all the link lanes out of reset.
0098
0099       "#phy-cells":
0100         const: 0
0101
0102       cdns,phy-type:
0103         description:
0104           Specifies the type of PHY for which the group of PHY lanes is used.
0105           Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
0106         $ref: /schemas/types.yaml#/definitions/uint32
0107         enum: [2, 4]
0108
0109       cdns,num-lanes:
0110         description:
0111           Number of lanes in this group. The group is made up of consecutive lanes.
0112         $ref: /schemas/types.yaml#/definitions/uint32
0113         minimum: 1
0114         maximum: 16
0115
0116       cdns,ssc-mode:
0117         description:
0118           Specifies the Spread Spectrum Clocking mode used. It can be NO_SSC,
0119           EXTERNAL_SSC or INTERNAL_SSC.
0120           Refer include/dt-bindings/phy/phy-cadence.h for the constants to be used.
0121         $ref: /schemas/types.yaml#/definitions/uint32
0122         enum: [0, 1, 2]
0123         default: 1
0124
0125     required:
0126       - reg
0127       - resets
0128       - "#phy-cells"
0129
0130     additionalProperties: false
0131
0132 required:
0133   - compatible
0134   - "#address-cells"
0135   - "#size-cells"
0136   - reg
0137   - resets
0138   - reset-names
0139
0140 additionalProperties: false
0141
0142 examples:
0143   - |
0144     #include <dt-bindings/phy/phy.h>
0145
0146     bus {
0147         #address-cells = <2>;
0148         #size-cells = <2>;
0149
0150         sierra-phy@fd240000 {
0151             compatible = "cdns,sierra-phy-t0";
0152             reg = <0x0 0xfd240000 0x0 0x40000>;
0153             resets = <&phyrst 0>, <&phyrst 1>;
0154             reset-names = "sierra_reset", "sierra_apb";
0155             clocks = <&cmn_refclk_dig_div>, <&cmn_refclk1_dig_div>;
0156             clock-names = "cmn_refclk_dig_div", "cmn_refclk1_dig_div";
0157             #address-cells = <1>;
0158             #size-cells = <0>;
0159             pcie0_phy0: phy@0 {
0160                 reg = <0>;
0161                 resets = <&phyrst 2>;
0162                 cdns,num-lanes = <2>;
0163                 #phy-cells = <0>;
0164                 cdns,phy-type = <PHY_TYPE_PCIE>;
0165             };
0166             pcie0_phy1: phy@2 {
0167                 reg = <2>;
0168                 resets = <&phyrst 4>;
0169                 cdns,num-lanes = <1>;
0170                 #phy-cells = <0>;
0171                 cdns,phy-type = <PHY_TYPE_PCIE>;
0172             };
0173         };
0174     };